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Searched refs:ShiftOp (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/Transforms/InstCombine/
DInstCombineShifts.cpp543 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); in FoldShiftByConstant() local
544 if (ShiftOp && !ShiftOp->isShift()) in FoldShiftByConstant()
545 ShiftOp = nullptr; in FoldShiftByConstant()
547 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) { in FoldShiftByConstant()
561 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1)); in FoldShiftByConstant()
566 Value *X = ShiftOp->getOperand(0); in FoldShiftByConstant()
571 if (I.getOpcode() == ShiftOp->getOpcode()) { in FoldShiftByConstant()
588 ShiftOp->getOpcode() == Instruction::Shl) { in FoldShiftByConstant()
600 ShiftOp->getOpcode() != Instruction::Shl && in FoldShiftByConstant()
601 ShiftOp->isExact()) { in FoldShiftByConstant()
[all …]
/external/swiftshader/third_party/subzero/src/
DIceInstARM32.h114 Variable *Index, ShiftKind ShiftOp = kNoShift,
118 OperandARM32Mem(Func, Ty, Base, Index, ShiftOp, ShiftAmt, Mode);
123 ShiftKind getShiftOp() const { return ShiftOp; } in getShiftOp()
155 ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode);
160 ShiftKind ShiftOp; variable
311 ShiftKind ShiftOp, Operand *ShiftAmt) { in create() argument
313 OperandARM32FlexReg(Func, Ty, Reg, ShiftOp, ShiftAmt); in create()
325 ShiftKind getShiftOp() const { return ShiftOp; } in getShiftOp()
330 OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp,
334 ShiftKind ShiftOp; variable
DIceInstARM32.cpp323 ShiftOp(kNoShift), ShiftAmt(0), Mode(Mode) { in OperandARM32Mem()
331 Variable *Index, ShiftKind ShiftOp, in OperandARM32Mem() argument
334 ShiftOp(ShiftOp), ShiftAmt(ShiftAmt), Mode(Mode) { in OperandARM32Mem()
471 ShiftKind ShiftOp, Operand *ShiftAmt) in OperandARM32FlexReg() argument
472 : OperandARM32Flex(kFlexReg, Ty), Reg(Reg), ShiftOp(ShiftOp), in OperandARM32FlexReg()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp694 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
695 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
696 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp692 unsigned ShiftOp; in PromoteIntRes_ADDSUBSAT() local
696 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSAT()
700 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSAT()
717 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
776 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX() local
777 return DAG.getNode(ShiftOp, dl, PromotedType, Result, in PromoteIntRes_MULFIX()
3354 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
3359 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
3360 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
3362 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
DDAGCombiner.cpp2052 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubOfSignBit() local
2054 if (!C || ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2058 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2063 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2064 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
6473 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
6474 if (!ShiftOp) in calculateByteProvider()
6477 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
7244 auto matchFirstShift = [&](SDValue V, SDValue &ShiftOp, in combineShiftOfShiftedLogic()
7254 ShiftOp = V.getOperand(0); in combineShiftOfShiftedLogic()
DSelectionDAGBuilder.cpp2719 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2728 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2734 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2739 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp774 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
775 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
776 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
/external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp774 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
775 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
776 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp757 unsigned ShiftOp; in PromoteIntRes_ADDSUBSHLSAT() local
762 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
767 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
785 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
844 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX() local
845 return DAG.getNode(ShiftOp, dl, PromotedType, Result, in PromoteIntRes_MULFIX()
3719 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
3724 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
3725 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
3727 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
DDAGCombiner.cpp2236 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubOfSignBit() local
2238 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2242 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2247 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2248 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
6988 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
6989 if (!ShiftOp) in calculateByteProvider()
6992 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
7802 auto matchFirstShift = [&](SDValue V, SDValue &ShiftOp, in combineShiftOfShiftedLogic()
7812 ShiftOp = V.getOperand(0); in combineShiftOfShiftedLogic()
DSelectionDAGBuilder.cpp2693 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2702 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2708 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2713 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp1859 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
1860 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp1904 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
1905 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp2362 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
2367 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2368 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
2370 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
DSelectionDAGBuilder.cpp2201 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2210 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2216 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2221 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
/external/capstone/arch/ARM/
DARMInstPrinter.c1436 unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); in printShiftImmOperand() local
1437 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
1438 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3228 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3273 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3341 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3386 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3342 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3387 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp6198 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; in lowerSMULH_UMULH() local
6201 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp201 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
205 setOperationAction(ShiftOp , MVT::i8 , Custom); in X86TargetLowering()
206 setOperationAction(ShiftOp , MVT::i16 , Custom); in X86TargetLowering()
207 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction); in X86TargetLowering()
209 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction); in X86TargetLowering()
44064 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
44065 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
44069 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp208 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
209 setOperationAction(ShiftOp , MVT::i16 , Custom); in X86TargetLowering()
210 setOperationAction(ShiftOp , MVT::i32 , Custom); in X86TargetLowering()
212 setOperationAction(ShiftOp , MVT::i64 , Custom); in X86TargetLowering()
40859 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
40860 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
40864 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp28576 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
28577 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
28581 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()