| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64PostLegalizerCombiner.cpp | 209 auto ShiftedVal = B.buildShl(Ty, LHS, Shift); in matchAArch64MulConstCombine() local
211 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS; in matchAArch64MulConstCombine()
212 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0); in matchAArch64MulConstCombine()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 3834 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) { in tryShrinkShlLogicImm() argument
3838 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
3839 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
3842 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) in tryShrinkShlLogicImm()
3845 ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm()
3846 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || in tryShrinkShlLogicImm()
3847 (!isInt<32>(Val) && isInt<32>(ShiftedVal))) in tryShrinkShlLogicImm()
3851 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
3852 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
3858 int64_t ShiftedVal; in tryShrinkShlLogicImm() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 826 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImm() local
827 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff; in isAddSubImm()
839 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImmNeg() local
840 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff; in isAddSubImmNeg()
1540 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmWithOptionalShiftOperands() local
1541 Inst.addOperand(MCOperand::createImm(ShiftedVal->first)); in addImmWithOptionalShiftOperands()
1542 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmWithOptionalShiftOperands()
1555 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmNegWithOptionalShiftOperands() local
1556 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first)); in addImmNegWithOptionalShiftOperands()
1557 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmNegWithOptionalShiftOperands()
|
| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 861 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImm() local
862 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff; in isAddSubImm()
874 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImmNeg() local
875 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff; in isAddSubImmNeg()
1581 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmWithOptionalShiftOperands() local
1582 Inst.addOperand(MCOperand::createImm(ShiftedVal->first)); in addImmWithOptionalShiftOperands()
1583 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmWithOptionalShiftOperands()
1596 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmNegWithOptionalShiftOperands() local
1597 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first)); in addImmNegWithOptionalShiftOperands()
1598 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmNegWithOptionalShiftOperands()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 3933 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) { in tryShrinkShlLogicImm() argument
3937 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
3938 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
3941 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) in tryShrinkShlLogicImm()
3944 ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm()
3945 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || in tryShrinkShlLogicImm()
3946 (!isInt<32>(Val) && isInt<32>(ShiftedVal))) in tryShrinkShlLogicImm()
3950 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
3951 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
3957 int64_t ShiftedVal; in tryShrinkShlLogicImm() local
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 7557 SDValue ShiftedVal = in performMulCombine() local
7560 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, in performMulCombine()
7566 SDValue ShiftedVal = in performMulCombine() local
7569 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal, in performMulCombine()
7576 SDValue ShiftedVal = in performMulCombine() local
7580 ShiftedVal); in performMulCombine()
7585 SDValue ShiftedVal = in performMulCombine() local
7589 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0)); in performMulCombine()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 3750 APInt ShiftedVal = N1C->getAPIntValue().lshr(Shift); in getNode() local
3751 return getConstant(ShiftedVal.trunc(ElementSize), DL, VT); in getNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9837 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0, in performMulCombine() local
9840 SDValue AddSubN0 = ShiftValUseIsN0 ? ShiftedVal : N0; in performMulCombine()
9841 SDValue AddSubN1 = ShiftValUseIsN0 ? N0 : ShiftedVal; in performMulCombine()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5407 APInt ShiftedVal = N1C->getAPIntValue().lshr(Shift); in getNode() local
5408 return getConstant(ShiftedVal.trunc(ElementSize), DL, VT); in getNode()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 5503 APInt ShiftedVal = N1C->getAPIntValue().lshr(Shift); in getNode() local
5504 return getConstant(ShiftedVal.trunc(ElementSize), DL, VT); in getNode()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 11699 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0, in performMulCombine() local
11702 SDValue AddSubN0 = ShiftValUseIsN0 ? ShiftedVal : N0; in performMulCombine()
11703 SDValue AddSubN1 = ShiftValUseIsN0 ? N0 : ShiftedVal; in performMulCombine()
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