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Searched refs:SignExt (Results 1 – 18 of 18) sorted by relevance

/external/llvm-project/clang/include/clang/CodeGen/
DCGFunctionInfo.h111 bool SignExt : 1; // isExtend() variable
133 SignExt(false) {} in TypeData()
311 return SignExt; in isSignExt()
315 SignExt = SExt; in setSignExt()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp3990 PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, in isSignOrZeroExtended() argument
3997 if (SignExt ? isSignExtendingOp(MI): in isSignOrZeroExtended()
4014 return SignExt ? FuncInfo->isLiveInSExt(VReg) : in isSignOrZeroExtended()
4041 return Attrs.hasAttribute(SignExt ? Attribute::SExt : in isSignOrZeroExtended()
4053 return isSignOrZeroExtended(*SrcMI, SignExt, Depth); in isSignOrZeroExtended()
4077 return isSignOrZeroExtended(*SrcMI, SignExt, Depth); in isSignOrZeroExtended()
4105 if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1)) in isSignOrZeroExtended()
4136 if(SignExt) in isSignOrZeroExtended()
4137 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) && in isSignOrZeroExtended()
4138 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1); in isSignOrZeroExtended()
[all …]
DPPCInstrInfo.h406 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp4773 PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, in isSignOrZeroExtended() argument
4780 if (SignExt ? isSignExtendingOp(MI): in isSignOrZeroExtended()
4797 return SignExt ? FuncInfo->isLiveInSExt(VReg) : in isSignOrZeroExtended()
4824 return Attrs.hasAttribute(SignExt ? Attribute::SExt : in isSignOrZeroExtended()
4836 return isSignOrZeroExtended(*SrcMI, SignExt, Depth); in isSignOrZeroExtended()
4860 return isSignOrZeroExtended(*SrcMI, SignExt, Depth); in isSignOrZeroExtended()
4888 if (SrcMI == NULL || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1)) in isSignOrZeroExtended()
4919 if(SignExt) in isSignOrZeroExtended()
4920 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) && in isSignOrZeroExtended()
4921 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1); in isSignOrZeroExtended()
[all …]
DPPCInstrInfo.h570 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp2496 static bool SearchSignedMulShort(SDValue SignExt, unsigned *Opc, SDValue &Src1, in SearchSignedMulShort() argument
2501 if ((SignExt.getOpcode() == ISD::SIGN_EXTEND || in SearchSignedMulShort()
2502 SignExt.getOpcode() == ISD::SIGN_EXTEND_INREG || in SearchSignedMulShort()
2503 SignExt.getOpcode() == ISD::AssertSext) && in SearchSignedMulShort()
2504 SignExt.getValueType() == MVT::i32) { in SearchSignedMulShort()
2507 Src1 = SignExt.getOperand(0); in SearchSignedMulShort()
2511 if (SignExt.getOpcode() != ISD::SRA) in SearchSignedMulShort()
2514 ConstantSDNode *SRASrc1 = dyn_cast<ConstantSDNode>(SignExt.getOperand(1)); in SearchSignedMulShort()
2518 SDValue Op0 = SignExt.getOperand(0); in SearchSignedMulShort()
2532 Src1 = SignExt.getOperand(0); in SearchSignedMulShort()
/external/llvm-project/llvm/lib/Transforms/Utils/
DSimplifyIndVar.cpp1254 auto GuessNonIVOperand = [&](bool SignExt) { in cloneArithmeticIVUser() argument
1258 auto GetExtend = [this, SignExt](const SCEV *S, Type *Ty) { in cloneArithmeticIVUser()
1259 if (SignExt) in cloneArithmeticIVUser()
/external/llvm/lib/Transforms/Scalar/
DIndVarSimplify.cpp1034 auto GuessNonIVOperand = [&](bool SignExt) { in cloneArithmeticIVUser() argument
1038 auto GetExtend = [this, SignExt](const SCEV *S, Type *Ty) { in cloneArithmeticIVUser()
1039 if (SignExt) in cloneArithmeticIVUser()
/external/swiftshader/third_party/subzero/src/
DIceInstMIPS32.cpp37 bool OperandMIPS32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) { in canHoldOffset() argument
38 (void)SignExt; in canHoldOffset()
DIceTargetLoweringMIPS32.cpp1807 constexpr bool SignExt = true; in newBaseRegister() local
1808 if (!OperandMIPS32Mem::canHoldOffset(Base->getType(), SignExt, Offset)) { in newBaseRegister()
2123 constexpr bool SignExt = true; in legalizeMemOperand() local
2124 if (!OperandMIPS32Mem::canHoldOffset(Mem->getType(), SignExt, Offset)) { in legalizeMemOperand()
2303 constexpr bool SignExt = false; in hiOperand() local
2304 if (!OperandMIPS32Mem::canHoldOffset(SplitType, SignExt, NextOffsetVal)) { in hiOperand()
3451 constexpr bool SignExt = false; in lowerCall() local
3452 if (OperandMIPS32Mem::canHoldOffset(Ty, SignExt, StackArg.second)) { in lowerCall()
DIceInstARM32.cpp347 bool OperandARM32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) { in canHoldOffset() argument
348 int32_t Bits = SignExt ? TypeARM32Attributes[Ty].SExtAddrOffsetBits in canHoldOffset()
DIceInstMIPS32.h150 static bool canHoldOffset(Type Ty, bool SignExt, int32_t Offset);
DIceInstARM32.h149 static bool canHoldOffset(Type Ty, bool SignExt, int32_t Offset);
DIceTargetLoweringARM32.cpp3761 constexpr bool SignExt = false; in lowerCall() local
3762 if (OperandARM32Mem::canHoldOffset(Ty, SignExt, StackArg.second)) { in lowerCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DIndVarSimplify.cpp1159 auto GuessNonIVOperand = [&](bool SignExt) { in cloneArithmeticIVUser() argument
1163 auto GetExtend = [this, SignExt](const SCEV *S, Type *Ty) { in cloneArithmeticIVUser()
1164 if (SignExt) in cloneArithmeticIVUser()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp22513 SDValue SignExt = Curr; in LowerEXTEND_VECTOR_INREG() local
22536 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()
22544 SignExt = DAG.getVectorShuffle(MVT::v4i32, dl, SignExt, Sign, {0, 4, 1, 5}); in LowerEXTEND_VECTOR_INREG()
22545 SignExt = DAG.getBitcast(VT, SignExt); in LowerEXTEND_VECTOR_INREG()
22548 return SignExt; in LowerEXTEND_VECTOR_INREG()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp23742 SDValue SignExt = Curr; in LowerEXTEND_VECTOR_INREG() local
23765 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()
23773 SignExt = DAG.getVectorShuffle(MVT::v4i32, dl, SignExt, Sign, {0, 4, 1, 5}); in LowerEXTEND_VECTOR_INREG()
23774 SignExt = DAG.getBitcast(VT, SignExt); in LowerEXTEND_VECTOR_INREG()
23777 return SignExt; in LowerEXTEND_VECTOR_INREG()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp16095 SDValue SignExt = Curr; in LowerSIGN_EXTEND_VECTOR_INREG() local
16099 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr, in LowerSIGN_EXTEND_VECTOR_INREG()
16104 return SignExt; in LowerSIGN_EXTEND_VECTOR_INREG()
16109 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5}); in LowerSIGN_EXTEND_VECTOR_INREG()