Home
last modified time | relevance | path

Searched refs:Skylake (Results 1 – 22 of 22) sorted by relevance

/external/angle/src/libANGLE/renderer/
Ddriver_utils.cpp57 const uint32_t Skylake[] = {0x1902, 0x1906, 0x190A, 0x190B, 0x190E, 0x1912, 0x1913, 0x1915, 0x1916, variable
121 return std::find(std::begin(Skylake), std::end(Skylake), DeviceId) != std::end(Skylake); in IsSkylake()
/external/llvm-project/llvm/test/CodeGen/X86/
Dbitcnt-false-dep.ll89 ; This false dependecy issue was fixed in Skylake
116 ; This false dependecy issue was fixed in Skylake
143 ; This false dependecy issue was fixed in Skylake
170 ; This false dependecy issue was fixed in Skylake
Dclwb.ll2 ; NOTE: clwb is available in Skylake Server, not available in the newer
Davx512-masked_memop-16-8.ll4 ; Skylake-avx512 target supports masked load/store for i8 and i16 vectors
/external/mesa3d/docs/_extra/specs/
DINTEL_shader_atomic_float_minmax.txt179 Further details are available in the Skylake Programmer's Reference
187 Due to a known issue in shipping Skylake GPUs, the incorrectly signed 0 is
/external/mesa3d/docs/relnotes/
D10.6.6.rst112 Skylake."
D13.0.4.rst55 != 0 on Skylake
D17.2.0.rst139 - [bisected] [Skylake] Kwin won't start and glxgears coredumps
D17.0.0.rst226 != 0 on Skylake
D13.0.0.rst29 - OpenGL ES 3.2 on i965/gen9+ (Skylake and later)
D19.0.0.rst1265 - anv: Advertise support for MinLod on Skylake+
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86.td375 // Skylake Client processor has faster Gathers than HSW and performance is
376 // similar to Skylake Server (AVX-512).
596 // Skylake
610 // Skylake-AVX512
DX86SchedSkylakeClient.td1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
9 // This file defines the machine model for Skylake Client to support
32 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
1751 // section "Skylake Pipeline" > "Register allocation and renaming".
DX86SchedSkylakeServer.td1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
9 // This file defines the machine model for Skylake Server to support
32 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
2467 // section "Skylake Pipeline" > "Register allocation and renaming".
/external/llvm-project/llvm/lib/Target/X86/
DX86.td409 // Skylake Client processor has faster Gathers than HSW and performance is
410 // similar to Skylake Server (AVX-512).
652 // Skylake
672 // Skylake-AVX512
DX86SchedSkylakeClient.td1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
9 // This file defines the machine model for Skylake Client to support
32 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
1752 // section "Skylake Pipeline" > "Register allocation and renaming".
DX86SchedSkylakeServer.td1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
9 // This file defines the machine model for Skylake Server to support
32 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
2455 // section "Skylake Pipeline" > "Register allocation and renaming".
/external/llvm/docs/
DReleaseNotes.rst135 * LLVM now supports the Intel CPU codenamed Skylake Server with AVX-512
/external/tensorflow/tensorflow/lite/micro/examples/micro_speech/train/
DREADME.md191 --min-cpu-platform=Intel\ Skylake
/external/llvm-project/llvm/docs/CommandGuide/
Dllvm-exegesis.rst191 `latency[LBR]` is only available on X86 (at least `Skylake`).
/external/llvm-project/lldb/tools/intel-features/intel-pt/
DREADME_TOOL.txt65 and other succeeding CPUs such as Skylake etc. In order for Tool to provide
/external/igt-gpu-tools/
DNEWS646 - Skylake and Broadwell support added to gem_gpgpu_fill tests.