Searched refs:Src0Bank (Results 1 – 3 of 3) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 610 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT() local
613 TRI.getRegClassForSizeOnBank(DstSize, *Src0Bank, *MRI); in selectG_INSERT()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 1380 const RegisterBank *Src0Bank = RBI.getRegBank(Src0, *MRI, *RBI.TRI); in setBufferOffsets() local
1383 if (Src0Bank == &AMDGPU::VGPRRegBank && Src1Bank == &AMDGPU::SGPRRegBank) { in setBufferOffsets()
1389 if (Src0Bank == &AMDGPU::SGPRRegBank && Src1Bank == &AMDGPU::VGPRRegBank) { in setBufferOffsets()
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| D | AMDGPUInstructionSelector.cpp | 725 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT() local
728 TRI.getRegClassForSizeOnBank(DstSize, *Src0Bank, *MRI); in selectG_INSERT()
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