| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 unsigned DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
58 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
64 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
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| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
58 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
64 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 566 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
581 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 880 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg() local
882 unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi)); in copyPhysReg()
884 .addReg(SrcHi, KillFlag | UndefHi) in copyPhysReg()
1055 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo() local
1058 unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi)); in expandPostRAPseudo()
1061 .addReg(SrcHi, UndefHi) in expandPostRAPseudo()
1325 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1329 .addReg(SrcHi) in expandPostRAPseudo()
1337 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1341 .addReg(SrcHi) in expandPostRAPseudo()
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| D | HexagonFrameLowering.cpp | 1933 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2() local
1959 if (LPR.contains(SrcHi)) { in expandStoreVec2()
1965 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 725 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
740 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 739 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
754 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1784 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2() local
1810 if (LPR.contains(SrcHi)) { in expandStoreVec2()
1816 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
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| D | HexagonInstrInfo.cpp | 1303 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1307 .addReg(SrcHi) in expandPostRAPseudo()
1315 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1319 .addReg(SrcHi) in expandPostRAPseudo()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1279 unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_hireg); in expandPostRAPseudo() local
1283 .addReg(SrcHi) in expandPostRAPseudo()
1286 SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_hireg); in expandPostRAPseudo()
1290 .addReg(SrcHi) in expandPostRAPseudo()
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| D | HexagonFrameLowering.cpp | 1551 unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::subreg_hireg); in expandStoreVec2() local
1586 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX86BaseImpl.h | 6776 Operand *SrcHi = hiOperand(Src);
6782 _mov(T_Hi, SrcHi);
7292 Operand *SrcHi = legalize(hiOperand(Src), Legal_Reg | Legal_Imm);
7301 _adc_rmw(AddrHi, SrcHi);
7305 _sbb_rmw(AddrHi, SrcHi);
7309 _and_rmw(AddrHi, SrcHi);
7313 _or_rmw(AddrHi, SrcHi);
7317 _xor_rmw(AddrHi, SrcHi);
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| D | IceInstARM32.cpp | 1928 auto *SrcHi = llvm::cast<Variable>(getSrc(1)); in emitSingleDestMultiSource() local
1930 assert(SrcHi->hasReg()); in emitSingleDestMultiSource()
1942 SrcHi->emit(Func); in emitSingleDestMultiSource()
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| D | IceTargetLoweringARM32.h | 314 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
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| D | IceTargetLoweringARM32.cpp | 2283 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) { in div0Check() argument
2284 if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi)) in div0Check()
2304 _orrs(T, SrcLoReg, legalize(SrcHi, Legal_Reg | Legal_Flex)); in div0Check()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 6097 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN() local
6099 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 6721 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN() local
6723 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ); in LowerINTRINSIC_WO_CHAIN()
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