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Searched refs:SrcIdx (Results 1 – 25 of 56) sorted by relevance

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/external/llvm-project/clang/lib/CodeGen/
DCGNonTrivialStruct.cpp33 enum { DstIdx = 0, SrcIdx = 1 }; enumerator
527 Address SrcAddr = this->getAddrWithOffset(Addrs[SrcIdx], this->Start); in flushTrivialFields()
566 Address SrcAddr = this->getAddrWithOffset(Addrs[SrcIdx], Offset); in visitVolatileTrivial()
573 Address SrcAddr = this->CGF->Builder.CreateBitCast(Addrs[SrcIdx], Ty); in visitVolatileTrivial()
690 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCStrong()
692 Addrs[SrcIdx], QT.isVolatileQualified(), QT, SourceLocation()); in visitARCStrong()
700 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], CurStructOffset, FD); in visitARCWeak()
701 CGF->EmitARCCopyWeak(Addrs[DstIdx], Addrs[SrcIdx]); in visitARCWeak()
707 Addrs[SrcIdx] = getAddrWithOffset(Addrs[SrcIdx], Offset); in callSpecialFunction()
709 CGF->MakeAddrLValue(Addrs[SrcIdx], FT)); in callSpecialFunction()
[all …]
/external/llvm/lib/CodeGen/
DRegisterCoalescer.h42 unsigned SrcIdx; variable
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair()
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
109 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
DTwoAddressInstructionPass.cpp132 unsigned SrcIdx, unsigned DstIdx,
1211 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1218 unsigned regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1227 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1253 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1408 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1410 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1413 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1427 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1435 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
[all …]
DRegisterCoalescer.cpp315 SrcIdx = DstIdx = 0; in setRegisters()
362 SrcIdx, DstIdx); in setRegisters()
367 SrcIdx = DstSub; in setRegisters()
384 if (DstIdx && !SrcIdx) { in setRegisters()
386 std::swap(SrcIdx, DstIdx); in setRegisters()
405 std::swap(SrcIdx, DstIdx); in flip()
429 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
443 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
885 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
927 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
[all …]
DTargetRegisterInfo.cpp299 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
302 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegisterCoalescer.h40 unsigned SrcIdx = 0; variable
104 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
DTwoAddressInstructionPass.cpp156 unsigned SrcIdx, unsigned DstIdx,
1271 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1278 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1287 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1313 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1467 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1469 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1472 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1486 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1494 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
[all …]
DRegisterCoalescer.cpp428 SrcIdx = DstIdx = 0; in setRegisters()
475 SrcIdx, DstIdx); in setRegisters()
480 SrcIdx = DstSub; in setRegisters()
497 if (DstIdx && !SrcIdx) { in setRegisters()
499 std::swap(SrcIdx, DstIdx); in setRegisters()
518 std::swap(SrcIdx, DstIdx); in flip()
542 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
556 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
1238 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
1281 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
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DPeepholeOptimizer.cpp1845 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1846 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1855 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1858 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1863 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1873 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
/external/llvm-project/llvm/lib/CodeGen/
DRegisterCoalescer.h42 unsigned SrcIdx = 0; variable
106 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
DTwoAddressInstructionPass.cpp146 unsigned SrcIdx, unsigned DstIdx,
1127 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1134 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1142 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1168 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1322 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1324 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1327 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1341 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1349 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
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DRegisterCoalescer.cpp428 SrcIdx = DstIdx = 0; in setRegisters()
476 SrcIdx, DstIdx); in setRegisters()
481 SrcIdx = DstSub; in setRegisters()
498 if (DstIdx && !SrcIdx) { in setRegisters()
500 std::swap(SrcIdx, DstIdx); in setRegisters()
519 std::swap(SrcIdx, DstIdx); in flip()
544 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
558 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
1252 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
1295 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
[all …]
DPeepholeOptimizer.cpp1845 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1846 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1855 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1858 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1863 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1873 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dmma-acc-memops.ll12 define void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
46 define void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
82 %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %SrcIdx
134 define void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
160 define void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
188 %arrayidx = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %SrcIdx
/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h108 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
312 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
DR600InstrInfo.cpp262 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
278 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
323 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs() local
324 if (SrcIdx < 0) in getSrcs()
326 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1427 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1449 switch (SrcIdx) { in getFlagOp()
1466 switch (SrcIdx) { in getFlagOp()
DR600ISelLowering.h94 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h112 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
310 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
DR600InstrInfo.cpp254 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
270 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
315 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs() local
316 if (SrcIdx < 0) in getSrcs()
318 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1401 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1423 switch (SrcIdx) { in getFlagOp()
1440 switch (SrcIdx) { in getFlagOp()
DR600ISelLowering.h101 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h112 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
310 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
DR600InstrInfo.cpp254 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
270 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
315 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs() local
316 if (SrcIdx < 0) in getSrcs()
318 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1400 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1422 switch (SrcIdx) { in getFlagOp()
1439 switch (SrcIdx) { in getFlagOp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp2275 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
2284 SrcIdx = 1; MaskIdx = 5; break; in EmitInstruction()
2288 SrcIdx = 2; MaskIdx = 6; break; in EmitInstruction()
2292 SrcIdx = 3; MaskIdx = 7; break; in EmitInstruction()
2304 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in EmitInstruction()
2333 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
2342 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break; in EmitInstruction()
2346 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break; in EmitInstruction()
2350 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break; in EmitInstruction()
2356 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break; in EmitInstruction()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86MCInstLower.cpp2015 unsigned SrcIdx = 1; in addConstantComments() local
2018 ++SrcIdx; in addConstantComments()
2021 ++SrcIdx; in addConstantComments()
2024 unsigned MaskIdx = SrcIdx + 1 + X86::AddrDisp; in addConstantComments()
2026 assert(MI->getNumOperands() >= (SrcIdx + 1 + X86::AddrNumOperands) && in addConstantComments()
2035 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in addConstantComments()
2093 unsigned SrcIdx = 1; in addConstantComments() local
2096 ++SrcIdx; in addConstantComments()
2099 ++SrcIdx; in addConstantComments()
2102 unsigned MaskIdx = SrcIdx + 1 + X86::AddrDisp; in addConstantComments()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DInferAddressSpaces.cpp961 int SrcIdx = U.getOperandNo(); in rewriteWithNewAddressSpaces() local
962 int OtherIdx = (SrcIdx == 0) ? 1 : 0; in rewriteWithNewAddressSpaces()
968 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
976 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()

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