Searched refs:SrcIsZero (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 1885 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0, Hi0); in LowerCTLZ() local
1897 SrcIsZero, Bits32, NewCtlz); in LowerCTLZ()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 6731 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); in expandCTLZ() local
6732 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, in expandCTLZ()
6783 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); in expandCTTZ() local
6784 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, in expandCTTZ()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 6452 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); in expandCTLZ() local
6453 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, in expandCTLZ()
6504 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); in expandCTTZ() local
6505 Result = DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, in expandCTTZ()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 2694 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ); in ExpandBitCount() local
2695 return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero, in ExpandBitCount()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 2378 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0); in LowerCTLZ_CTTZ() local
2390 SrcIsZero, Bits32, NewOpr); in LowerCTLZ_CTTZ()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 2376 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0); in LowerCTLZ_CTTZ() local
2388 SrcIsZero, Bits32, NewOpr); in LowerCTLZ_CTTZ()
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