| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 unsigned DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
58 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
62 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
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| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
58 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
62 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 566 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
580 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 879 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg() local
881 unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo)); in copyPhysReg()
885 .addReg(SrcLo, KillFlag | UndefLo); in copyPhysReg()
1054 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo() local
1057 unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo)); in expandPostRAPseudo()
1062 .addReg(SrcLo, Kill | UndefLo); in expandPostRAPseudo()
1324 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1330 .addReg(SrcLo); in expandPostRAPseudo()
1336 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1342 .addReg(SrcLo); in expandPostRAPseudo()
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| D | HexagonFrameLowering.cpp | 1932 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2() local
1948 if (LPR.contains(SrcLo)) { in expandStoreVec2()
1954 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 725 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
739 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 739 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
753 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1783 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2() local
1799 if (LPR.contains(SrcLo)) { in expandStoreVec2()
1805 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
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| D | HexagonInstrInfo.cpp | 1302 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1308 .addReg(SrcLo); in expandPostRAPseudo()
1314 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo() local
1320 .addReg(SrcLo); in expandPostRAPseudo()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1278 unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_loreg); in expandPostRAPseudo() local
1284 .addReg(SrcLo); in expandPostRAPseudo()
1285 SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_loreg); in expandPostRAPseudo()
1291 .addReg(SrcLo); in expandPostRAPseudo()
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| D | HexagonFrameLowering.cpp | 1550 unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::subreg_loreg); in expandStoreVec2() local
1574 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX86BaseImpl.h | 6775 Operand *SrcLo = loOperand(Src);
6780 _mov(T_Lo, SrcLo);
7291 Operand *SrcLo = legalize(loOperand(Src), Legal_Reg | Legal_Imm);
7300 _add_rmw(AddrLo, SrcLo);
7304 _sub_rmw(AddrLo, SrcLo);
7308 _and_rmw(AddrLo, SrcLo);
7312 _or_rmw(AddrLo, SrcLo);
7316 _xor_rmw(AddrLo, SrcLo);
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| D | IceInstARM32.cpp | 1927 auto *SrcLo = llvm::cast<Variable>(getSrc(0)); in emitSingleDestMultiSource() local
1931 assert(SrcLo->hasReg()); in emitSingleDestMultiSource()
1940 SrcLo->emit(Func); in emitSingleDestMultiSource()
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| D | IceTargetLoweringARM32.h | 314 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
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| D | IceTargetLoweringARM32.cpp | 2283 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) { in div0Check() argument
2284 if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi)) in div0Check()
2286 Variable *SrcLoReg = legalizeToReg(SrcLo); in div0Check()
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