| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 119 class SrcOp {
129 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp() function
130 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} in SrcOp() function
131 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} in SrcOp() function
132 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} in SrcOp() function
136 SrcOp(unsigned) = delete;
137 SrcOp(int) = delete;
138 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
139 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
420 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
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| D | ConstantFoldingMIRBuilder.h | 29 ArrayRef<SrcOp> SrcOps,
50 const SrcOp &Src0 = SrcOps[0];
51 const SrcOp &Src1 = SrcOps[1];
61 const SrcOp &Src0 = SrcOps[0];
62 const SrcOp &Src1 = SrcOps[1];
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| D | CSEMIRBuilder.h | 63 void profileSrcOp(const SrcOp &Op, GISelInstProfileBuilder &B) const;
65 void profileSrcOps(ArrayRef<SrcOp> Ops, GISelInstProfileBuilder &B) const { in profileSrcOps()
66 for (const SrcOp &Op : Ops) in profileSrcOps()
73 ArrayRef<SrcOp> SrcOps, Optional<unsigned> Flags,
95 ArrayRef<SrcOp> SrcOps,
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 120 class SrcOp {
130 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp() function
131 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} in SrcOp() function
132 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} in SrcOp() function
133 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} in SrcOp() function
137 SrcOp(unsigned) = delete;
138 SrcOp(int) = delete;
139 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
140 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
381 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
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| D | ConstantFoldingMIRBuilder.h | 29 ArrayRef<SrcOp> SrcOps,
50 const SrcOp &Src0 = SrcOps[0];
51 const SrcOp &Src1 = SrcOps[1];
61 const SrcOp &Src0 = SrcOps[0];
62 const SrcOp &Src1 = SrcOps[1];
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| D | CSEMIRBuilder.h | 63 void profileSrcOp(const SrcOp &Op, GISelInstProfileBuilder &B) const;
65 void profileSrcOps(ArrayRef<SrcOp> Ops, GISelInstProfileBuilder &B) const { in profileSrcOps()
66 for (const SrcOp &Op : Ops) in profileSrcOps()
73 ArrayRef<SrcOp> SrcOps, Optional<unsigned> Flags,
95 ArrayRef<SrcOp> SrcOps,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 164 const SrcOp &Size, in buildDynStackAlloc()
215 const SrcOp &Op0, in buildPtrAdd()
216 const SrcOp &Op1) { in buildPtrAdd()
241 const SrcOp &Op0, in buildPtrMask()
274 const SrcOp &Op) { in buildCopy()
361 const SrcOp &Addr, in buildLoad()
368 const SrcOp &Addr, in buildLoadInstr()
380 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val, in buildStore()
381 const SrcOp &Addr, in buildStore()
395 const SrcOp &Op0, in buildUAddo()
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| D | CSEMIRBuilder.cpp | 70 void CSEMIRBuilder::profileSrcOp(const SrcOp &Op, in profileSrcOp()
73 case SrcOp::SrcType::Ty_Predicate: in profileSrcOp()
91 ArrayRef<SrcOp> SrcOps, in profileEverything()
139 ArrayRef<SrcOp> SrcOps, in buildInstr()
169 const SrcOp &Src0 = SrcOps[0]; in buildInstr()
170 const SrcOp &Src1 = SrcOps[1]; in buildInstr()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 127 const SrcOp &Size, in buildDynStackAlloc()
183 const SrcOp &Op0, in buildPtrAdd()
184 const SrcOp &Op1) { in buildPtrAdd()
209 const SrcOp &Op0, in buildMaskLowPtrBits()
239 const SrcOp &Op) { in buildCopy()
320 MachineInstrBuilder MachineIRBuilder::buildBrCond(const SrcOp &Tst, in buildBrCond()
331 MachineIRBuilder::buildLoad(const DstOp &Dst, const SrcOp &Addr, in buildLoad()
347 const SrcOp &Addr, in buildLoadInstr()
360 const DstOp &Dst, const SrcOp &BasePtr, in buildLoadFromOffset()
376 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val, in buildStore()
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| D | CSEMIRBuilder.cpp | 82 void CSEMIRBuilder::profileSrcOp(const SrcOp &Op, in profileSrcOp()
85 case SrcOp::SrcType::Ty_Imm: in profileSrcOp()
88 case SrcOp::SrcType::Ty_Predicate: in profileSrcOp()
106 ArrayRef<SrcOp> SrcOps, in profileEverything()
169 ArrayRef<SrcOp> SrcOps, in buildInstr()
199 const SrcOp &Src0 = SrcOps[0]; in buildInstr()
200 const SrcOp &Src1 = SrcOps[1]; in buildInstr()
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| /external/llvm-project/llvm/lib/Linker/ |
| D | IRMover.cpp | 1229 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1231 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1232 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1242 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1243 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1250 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1251 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1261 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1262 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
1269 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Linker/ |
| D | IRMover.cpp | 1227 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1229 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1230 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1240 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1241 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1248 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1249 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1259 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1260 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
1267 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
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| /external/llvm/lib/Linker/ |
| D | IRMover.cpp | 1045 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1047 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1048 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1058 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1059 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1066 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1067 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1080 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1086 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1087 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 465 for (const auto &SrcOp : Def->explicit_operands()) in findMaskOperands() local
466 if (SrcOp.isReg() && SrcOp.isUse() && in findMaskOperands()
467 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec)) in findMaskOperands()
468 Src.push_back(SrcOp); in findMaskOperands()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 215 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
624 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor() argument
628 MachineInstr *MI = SrcOp.getParent(); in genCondTfrFor()
638 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); in genCondTfrFor()
643 if (SrcOp.isReg()) { in genCondTfrFor()
644 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
645 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
650 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
655 .add(SrcOp); in genCondTfrFor()
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| D | HexagonRDFOpt.cpp | 139 const MachineOperand &SrcOp = MI->getOperand(1); in INITIALIZE_PASS_DEPENDENCY() local
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 213 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
623 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor() argument
627 MachineInstr *MI = SrcOp.getParent(); in genCondTfrFor()
637 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); in genCondTfrFor()
642 if (SrcOp.isReg()) { in genCondTfrFor()
643 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
644 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
649 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
654 .add(SrcOp); in genCondTfrFor()
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| D | HexagonRDFOpt.cpp | 139 const MachineOperand &SrcOp = MI->getOperand(1); in INITIALIZE_PASS_DEPENDENCY() local
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 123 const MachineOperand &SrcOp = MI->getOperand(1); in interpretAsCopy() local
125 { SrcOp.getReg(), SrcOp.getSubReg() }); in interpretAsCopy()
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| D | HexagonFrameLowering.cpp | 2108 MachineOperand &SrcOp = SI->getOperand(2); in optimizeSpillSlots() local
2110 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2111 SrcOp.getSubReg() }; in optimizeSpillSlots()
2112 auto *RC = getRegClass({SrcOp.getReg(), SrcOp.getSubReg()}); in optimizeSpillSlots()
2125 .addOperand(SrcOp); in optimizeSpillSlots()
2132 if (unsigned SR = SrcOp.getSubReg()) in optimizeSpillSlots()
2133 SrcOp.setReg(HRI.getSubReg(FoundR, SR)); in optimizeSpillSlots()
2135 SrcOp.setReg(FoundR); in optimizeSpillSlots()
2136 SrcOp.setSubReg(0); in optimizeSpillSlots()
2138 SrcOp.setIsKill(false); in optimizeSpillSlots()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 567 for (const auto &SrcOp : Def->explicit_operands()) in findMaskOperands() local
568 if (SrcOp.isReg() && SrcOp.isUse() && in findMaskOperands()
569 (SrcOp.getReg().isVirtual() || SrcOp.getReg() == Exec)) in findMaskOperands()
570 Src.push_back(SrcOp); in findMaskOperands()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 291 std::pair<unsigned,unsigned> SrcOp = (FirstIsDest ? RHSOp : LHSOp); in ParseConstraint() local
299 if (SrcOp.first < Ops.NumDefs) in ParseConstraint()
307 if (!Ops[SrcOp.first].Constraints[SrcOp.second].isNone()) in ParseConstraint()
325 Ops[SrcOp.first].Constraints[SrcOp.second] = NewConstraint; in ParseConstraint()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 244 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false); in ParseConstraint() local
245 if (SrcOp > DestOp) { in ParseConstraint()
246 std::swap(SrcOp, DestOp); in ParseConstraint()
250 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp); in ParseConstraint()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | MIRYamlMapping.h | 447 unsigned SrcOp;
452 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
453 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
460 YamlIO.mapRequired("srcop", Sub.SrcOp);
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1467 const MachineOperand &SrcOp = MI->getOperand(SrcIdx); in EmitInstruction() local
1474 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1489 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1496 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1511 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1518 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
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