Searched refs:SrcOp1 (Results 1 – 8 of 8) sorted by relevance
| /external/llvm-project/llvm/utils/TableGen/ |
| D | AsmMatcherEmitter.cpp | 1830 unsigned SrcOp1 = 0; in buildAliasResultOperands() local
1837 SrcOp1 = ResOperands[TiedOp].AsmOperandNum; in buildAliasResultOperands()
1840 StringRef Name = AsmOperands[SrcOp1].SrcOpName; in buildAliasResultOperands()
1841 auto Insert = OperandRefs.try_emplace(Name, SrcOp1); in buildAliasResultOperands()
1851 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2; in buildAliasResultOperands()
1860 SrcOp1 = ResOperands[TiedOp].AsmOperandNum; in buildAliasResultOperands()
1865 ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2)); in buildAliasResultOperands()
1867 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2)); in buildAliasResultOperands()
2159 uint8_t SrcOp1 = in emitConvertFuncs() local
2166 utostr(SrcOp1) + '_' + utostr(SrcOp2); in emitConvertFuncs()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1156 const MachineOperand &SrcOp1, in getShuffleComment() argument
1173 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; in getShuffleComment()
1532 const MachineOperand &SrcOp1 = MI->getOperand(1); in EmitInstruction() local
1551 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); in EmitInstruction()
1562 const MachineOperand &SrcOp1 = MI->getOperand(1); in EmitInstruction() local
1570 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); in EmitInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1772 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); in getShuffleComment() local
1777 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; in getShuffleComment()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1805 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx); in getShuffleComment() local
1810 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; in getShuffleComment()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4131 auto &SrcOp1 = Operands[OpndNum1];
4133 if (SrcOp1->isReg() && SrcOp2->isReg()) {
4134 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmMatcher.inc | 4906 auto &SrcOp1 = Operands[OpndNum1];
4908 if (SrcOp1->isReg() && SrcOp2->isReg()) {
4909 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12455 auto &SrcOp1 = Operands[OpndNum1];
12457 if (SrcOp1->isReg() && SrcOp2->isReg()) {
12458 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenAsmMatcher.inc | 7592 auto &SrcOp1 = Operands[OpndNum1];
7594 if (SrcOp1->isReg() && SrcOp2->isReg()) {
7595 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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