Searched refs:SrcOp2 (Results 1 – 8 of 8) sorted by relevance
| /external/llvm-project/llvm/utils/TableGen/ |
| D | AsmMatcherEmitter.cpp | 1831 unsigned SrcOp2 = 0; in buildAliasResultOperands() local
1842 SrcOp2 = findAsmOperandNamed(Name, Insert.first->second); in buildAliasResultOperands()
1847 Insert.first->second = SrcOp2; in buildAliasResultOperands()
1851 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2; in buildAliasResultOperands()
1863 SrcOp2 = findAsmOperand(Name, SubIdx); in buildAliasResultOperands()
1865 ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2)); in buildAliasResultOperands()
1867 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2)); in buildAliasResultOperands()
2161 uint8_t SrcOp2 = in emitConvertFuncs() local
2166 utostr(SrcOp1) + '_' + utostr(SrcOp2); in emitConvertFuncs()
2171 ConversionRow.push_back(SrcOp2); in emitConvertFuncs()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1157 const MachineOperand &SrcOp2, in getShuffleComment() argument
1175 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; in getShuffleComment()
1533 const MachineOperand &SrcOp2 = MI->getOperand(2); in EmitInstruction() local
1551 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); in EmitInstruction()
1563 const MachineOperand &SrcOp2 = MI->getOperand(2); in EmitInstruction() local
1570 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); in EmitInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1773 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); in getShuffleComment() local
1779 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; in getShuffleComment()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1806 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); in getShuffleComment() local
1812 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; in getShuffleComment()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4132 auto &SrcOp2 = Operands[OpndNum2];
4133 if (SrcOp1->isReg() && SrcOp2->isReg()) {
4134 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmMatcher.inc | 4907 auto &SrcOp2 = Operands[OpndNum2];
4908 if (SrcOp1->isReg() && SrcOp2->isReg()) {
4909 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12456 auto &SrcOp2 = Operands[OpndNum2];
12457 if (SrcOp1->isReg() && SrcOp2->isReg()) {
12458 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenAsmMatcher.inc | 7593 auto &SrcOp2 = Operands[OpndNum2];
7594 if (SrcOp1->isReg() && SrcOp2->isReg()) {
7595 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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