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Searched refs:SrcR (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DRDFCopy.cpp36 RegisterRef SrcR = { Src.getReg(), Src.getSubReg() }; in interpretAsCopy() local
38 if (!TargetRegisterInfo::isVirtualRegister(SrcR.Reg)) in interpretAsCopy()
41 if (MRI.getRegClass(DstR.Reg) != MRI.getRegClass(SrcR.Reg)) in interpretAsCopy()
44 if (!TargetRegisterInfo::isPhysicalRegister(SrcR.Reg)) in interpretAsCopy()
48 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
54 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
DHexagonGenInsert.cpp432 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {} in IFRecord()
433 unsigned SrcR, InsR; member
447 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
448 OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI) in operator <<()
488 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
637 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
640 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); in isValidInsertForm()
839 unsigned SrcR = *I; in findRecordInsertForms() local
841 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR); in findRecordInsertForms()
874 if (!isValidInsertForm(VR, SrcR, InsR, L, S)) in findRecordInsertForms()
[all …]
DHexagonRDFOpt.cpp98 auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in interpretAsCopy() argument
99 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
DHexagonFrameLowering.cpp1381 unsigned SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1383 !Hexagon::ModRegsRegClass.contains(SrcR)) in expandCopy()
1403 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1415 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1466 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1488 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1549 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1550 unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::subreg_loreg); in expandStoreVec2()
1551 unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::subreg_hireg); in expandStoreVec2()
1653 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp469 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {} in IFRecord()
471 unsigned SrcR, InsR; member
487 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
488 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<()
534 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
684 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
687 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); in isValidInsertForm()
881 unsigned SrcR = *I; in findRecordInsertForms() local
883 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR); in findRecordInsertForms()
916 if (!isValidInsertForm(VR, SrcR, InsR, L, S)) in findRecordInsertForms()
[all …]
DRDFCopy.cpp47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
49 assert(Register::isPhysicalRegister(SrcR.Reg)); in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
54 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
DHexagonRDFOpt.cpp113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY() argument
114 EM.insert(std::make_pair(DstR, SrcR)); in INITIALIZE_PASS_DEPENDENCY()
DHexagonFrameLowering.cpp1608 Register SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1610 !Hexagon::ModRegsRegClass.contains(SrcR)) in expandCopy()
1632 Register SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1642 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1695 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1711 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1782 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1783 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2()
1784 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2()
1882 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
[all …]
DHexagonBitSimplify.cpp2210 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
2219 if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i) in genBitSplit()
2238 if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR) in genBitSplit()
2255 if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I) in genBitSplit()
2270 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID) in genBitSplit()
2272 if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1)) in genBitSplit()
2282 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR) in genBitSplit()
2301 .addReg(SrcR, 0, SrcSR) in genBitSplit()
DHexagonConstPropagation.cpp1944 RegisterSubReg SrcR(MI.getOperand(1)); in evaluate() local
1945 bool Eval = evaluateCOPY(SrcR, Inputs, RC); in evaluate()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp469 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {} in IFRecord()
471 unsigned SrcR, InsR; member
487 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
488 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<()
534 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
684 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
687 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); in isValidInsertForm()
881 unsigned SrcR = *I; in findRecordInsertForms() local
883 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR); in findRecordInsertForms()
916 if (!isValidInsertForm(VR, SrcR, InsR, L, S)) in findRecordInsertForms()
[all …]
DRDFCopy.cpp47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
49 assert(Register::isPhysicalRegister(SrcR.Reg)); in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
54 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
DHexagonRDFOpt.cpp113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY() argument
114 EM.insert(std::make_pair(DstR, SrcR)); in INITIALIZE_PASS_DEPENDENCY()
DHexagonFrameLowering.cpp1757 Register SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1759 !Hexagon::ModRegsRegClass.contains(SrcR)) in expandCopy()
1781 Register SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1791 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1844 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1860 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1931 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1932 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo); in expandStoreVec2()
1933 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2()
2031 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
[all …]
DHexagonBitSimplify.cpp2220 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
2229 if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i) in genBitSplit()
2248 if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR) in genBitSplit()
2265 if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I) in genBitSplit()
2280 if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID) in genBitSplit()
2282 if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1)) in genBitSplit()
2292 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR) in genBitSplit()
2311 .addReg(SrcR, 0, SrcSR) in genBitSplit()
DHexagonConstPropagation.cpp1949 RegisterSubReg SrcR(MI.getOperand(1)); in evaluate() local
1950 bool Eval = evaluateCOPY(SrcR, Inputs, RC); in evaluate()
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringMIPS32.cpp1837 Variable *SrcR; in legalizeMovFp() local
1839 SrcR = Target->makeReg( in legalizeMovFp()
1842 SrcR = Target->makeReg( in legalizeMovFp()
1845 Sandboxer(Target).sw(SrcR, Addr); in legalizeMovFp()
1868 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
1869 if (Dest->hasReg() && SrcR->hasReg()) { in legalizeMov()
1874 const bool IsSrcGPR = RegMIPS32::isGPRReg(SrcR->getRegNum()); in legalizeMov()
1875 const RegNumT SRegNum = SrcR->getRegNum(); in legalizeMov()
1958 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
1959 assert(SrcR->hasReg()); in legalizeMov()
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DIceTargetLoweringARM32.cpp1867 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
1868 assert(SrcR->hasReg()); in legalizeMov()
1869 assert(!SrcR->isRematerializable()); in legalizeMov()
1873 SrcR, createMemOperand(DestTy, StackOrFrameReg, Offset), in legalizeMov()
/external/llvm/lib/Target/X86/
DX86FixupLEAs.cpp388 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM() local
391 .addOperand(SrcR) in processInstructionForSLM()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupLEAs.cpp517 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA() local
519 .add(SrcR) in processInstructionForSlowLEA()
/external/llvm-project/llvm/lib/Target/X86/
DX86FixupLEAs.cpp536 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA() local
538 .add(SrcR) in processInstructionForSlowLEA()