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Searched refs:SrcReg2 (Results 1 – 25 of 60) sorted by relevance

123

/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp180 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
188 SrcReg2 = 0; in analyzeCompare()
194 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
208 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
213 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
214 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
286 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
306 if (SrcReg2 != 0) in optimizeCompareInstr()
332 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
384 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
DLanaiInstrInfo.h95 unsigned &SrcReg2, int &CmpMask,
102 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp178 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = 0; in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
DLanaiInstrInfo.h98 unsigned &SrcReg2, int &CmpMask,
105 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp178 Register &SrcReg2, int &CmpMask, in analyzeCompare() argument
186 SrcReg2 = Register(); in analyzeCompare()
192 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
211 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
212 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/, in optimizeCompareInstr() argument
304 if (SrcReg2 != 0) in optimizeCompareInstr()
330 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
DLanaiInstrInfo.h99 Register &SrcReg2, int &CmpMask,
106 Register SrcReg2, int CmpMask, int CmpValue,
/external/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp407 unsigned SrcReg2 = in fuseCompareOperations() local
412 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareOperations()
459 if (SrcReg2) in fuseCompareOperations()
460 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareOperations()
DSystemZInstrInfo.h172 unsigned &SrcReg2, int &Mask, int &Value) const override;
174 unsigned SrcReg2, int Mask, int Value,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp631 Register SrcReg2 = in fuseCompareOperations() local
636 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareOperations()
688 if (SrcReg2) in fuseCompareOperations()
689 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareOperations()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp631 Register SrcReg2 = in fuseCompareOperations() local
636 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareOperations()
688 if (SrcReg2) in fuseCompareOperations()
689 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareOperations()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h250 unsigned &SrcReg2, int &Mask, int &Value) const override;
253 unsigned SrcReg2, int Mask, int Value,
DPPCFastISel.cpp876 unsigned SrcReg2 = 0; in PPCEmitCmp() local
878 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
879 if (SrcReg2 == 0) in PPCEmitCmp()
891 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
893 SrcReg2 = ExtReg; in PPCEmitCmp()
899 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1262 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1263 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1267 std::swap(SrcReg1, SrcReg2); in SelectBinaryIntOp()
1270 .addReg(SrcReg1).addReg(SrcReg2); in SelectBinaryIntOp()
DPPCInstrInfo.cpp1500 unsigned &SrcReg2, int &Mask, in analyzeCompare() argument
1511 SrcReg2 = 0; in analyzeCompare()
1522 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1528 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr() argument
1635 if (SrcReg2 != 0) in optimizeCompareInstr()
1672 Instr.getOperand(2).getReg() == SrcReg2) || in optimizeCompareInstr()
1673 (Instr.getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
1719 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h166 unsigned &SrcReg2, int &CmpMask,
171 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp859 unsigned SrcReg2 = 0; in PPCEmitCmp() local
861 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
862 if (SrcReg2 == 0) in PPCEmitCmp()
870 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; in PPCEmitCmp()
893 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2); in PPCEmitCmp()
943 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
945 SrcReg2 = ExtReg; in PPCEmitCmp()
951 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1362 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1363 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp857 unsigned SrcReg2 = 0; in PPCEmitCmp() local
859 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
860 if (SrcReg2 == 0) in PPCEmitCmp()
868 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; in PPCEmitCmp()
891 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2); in PPCEmitCmp()
941 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
943 SrcReg2 = ExtReg; in PPCEmitCmp()
949 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1359 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1360 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
[all …]
DPPCInstrInfo.h352 unsigned &SrcReg2, int &Mask, int &Value) const override;
355 unsigned SrcReg2, int Mask, int Value,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h209 unsigned &SrcReg2, int &CmpMask,
214 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMFastISel.cpp1428 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1430 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1431 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1439 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1440 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1447 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1449 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1776 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1777 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1781 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMFastISel.cpp1415 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1417 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1418 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1427 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1436 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1425 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1427 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1428 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1436 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1437 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1444 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1446 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
DARMBaseInstrInfo.h254 unsigned &SrcReg2, int &CmpMask,
262 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h222 Register &SrcReg2, int &CmpMask,
227 Register SrcReg2, int CmpMask, int CmpValue,
/external/llvm/lib/Target/X86/
DX86InstrInfo.h504 unsigned &SrcReg2, int &CmpMask,
511 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrInfo.h473 unsigned &SrcReg2, int &CmpMask,
480 unsigned SrcReg2, int CmpMask, int CmpValue,

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