Searched refs:SrcRegOp (Results 1 – 6 of 6) sorted by relevance
743 const MachineOperand *SrcRegOp, *DestRegOp; in removeEntryValue() local752 SrcRegOp = DestSrc->Source; in removeEntryValue()766 VL.MI.getOperand(0).getReg() == SrcRegOp->getReg()) in removeEntryValue()1122 const MachineOperand *SrcRegOp = DestSrc->Source; in transferRegisterCopy() local1134 Register SrcReg = SrcRegOp->getReg(); in transferRegisterCopy()1166 if (!SrcRegOp->isKill()) in transferRegisterCopy()
1017 const MachineOperand *SrcRegOp, *DestRegOp; in removeEntryValue() local1026 SrcRegOp = DestSrc->Source; in removeEntryValue()1037 VL.MI.getDebugOperand(0).getReg() == SrcRegOp->getReg()) in removeEntryValue()1444 const MachineOperand *SrcRegOp = DestSrc->Source; in transferRegisterCopy() local1456 Register SrcReg = SrcRegOp->getReg(); in transferRegisterCopy()1490 if (!SrcRegOp->isKill()) in transferRegisterCopy()
2018 const MachineOperand *SrcRegOp = DestSrc->Source; in transferRegisterCopy() local2027 Register SrcReg = SrcRegOp->getReg(); in transferRegisterCopy()2047 if (EmulateOldLDV && !SrcRegOp->isKill()) in transferRegisterCopy()2056 if (TTracker && isCalleeSavedReg(DestReg) && SrcRegOp->isKill()) in transferRegisterCopy()
4380 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUlh() local4381 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUlh()4387 unsigned SrcReg = SrcRegOp.getReg(); in expandUlh()4432 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUsh() local4433 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUsh()4439 unsigned SrcReg = SrcRegOp.getReg(); in expandUsh()4483 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUxw() local4484 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUxw()4490 unsigned SrcReg = SrcRegOp.getReg(); in expandUxw()
4352 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUlh() local4353 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUlh()4359 unsigned SrcReg = SrcRegOp.getReg(); in expandUlh()4404 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUsh() local4405 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUsh()4411 unsigned SrcReg = SrcRegOp.getReg(); in expandUsh()4455 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUxw() local4456 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUxw()4462 unsigned SrcReg = SrcRegOp.getReg(); in expandUxw()
3183 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUlh() local3184 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUlh()3190 unsigned SrcReg = SrcRegOp.getReg(); in expandUlh()3260 const MCOperand &SrcRegOp = Inst.getOperand(1); in expandUlw() local3261 assert(SrcRegOp.isReg() && "expected register operand kind"); in expandUlw()3266 unsigned SrcReg = SrcRegOp.getReg(); in expandUlw()