| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelDAGToDAG.cpp | 235 SDValue Srl = Or.getOperand(0); in SelectSROI() local
236 if (isa<ConstantSDNode>(Srl.getOperand(1)) && in SelectSROI()
240 uint64_t VC2 = Srl.getConstantOperandVal(1); in SelectSROI()
242 RS1 = Srl.getOperand(0); in SelectSROI()
244 Srl.getOperand(1).getValueType()); in SelectSROI()
250 uint32_t VC2 = Srl.getConstantOperandVal(1); in SelectSROI()
252 RS1 = Srl.getOperand(0); in SelectSROI()
254 Srl.getOperand(1).getValueType()); in SelectSROI()
354 SDValue Srl = N.getOperand(0); in SelectSROIW() local
355 if (Srl.getOpcode() != ISD::SRL || !isa<ConstantSDNode>(Srl.getOperand(1))) in SelectSROIW()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 357 def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
1029 def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>;
1032 def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>;
1035 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>;
1038 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>;
1042 def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>;
1045 def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>;
1154 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>;
1155 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>;
1156 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>;
[all …]
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 371 def Sub: pf2<sub>; def Or: pf2<or>; def Srl: pf2<srl>;
1062 def: OpR_RI_pat<S2_lsr_i_r, Srl, i32, I32, u5_0ImmPred>;
1065 def: OpR_RI_pat<S2_lsr_i_p, Srl, i64, I64, u6_0ImmPred>;
1068 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v4i16, V4I16, u4_0ImmPred>;
1071 def: OpR_RI_pat<S2_lsr_i_vh, Srl, v2i32, V2I32, u5_0ImmPred>;
1075 def: OpR_RR_pat<S2_lsr_r_r, Srl, i32, I32, I32>;
1078 def: OpR_RR_pat<S2_lsr_r_p, Srl, i64, I64, I32>;
1187 def: AccRRI_pat<S2_lsr_i_r_acc, Add, Su<Srl>, I32, u5_0ImmPred>;
1188 def: AccRRI_pat<S2_lsr_i_r_nac, Sub, Su<Srl>, I32, u5_0ImmPred>;
1189 def: AccRRI_pat<S2_lsr_i_r_and, And, Su<Srl>, I32, u5_0ImmPred>;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 350 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
351 if (Srl.getOpcode() == ISD::SRL) { in isExtractHiElt()
352 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt()
354 Out = stripBitcast(Srl.getOperand(0)); in isExtractHiElt()
1959 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
1960 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); in SelectS_BFE()
1971 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
|
| D | SIISelLowering.cpp | 9386 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
9388 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine()
9390 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, EltVT.changeTypeToInteger(), Srl); in performExtractVectorEltCombine()
9922 SDValue Srl = N->getOperand(0); in performCvtF32UByteNCombine() local
9923 if (Srl.getOpcode() == ISD::ZERO_EXTEND) in performCvtF32UByteNCombine()
9924 Srl = Srl.getOperand(0); in performCvtF32UByteNCombine()
9927 if (Srl.getOpcode() == ISD::SRL) { in performCvtF32UByteNCombine()
9933 dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in performCvtF32UByteNCombine()
9934 Srl = DAG.getZExtOrTrunc(Srl.getOperand(0), SDLoc(Srl.getOperand(0)), in performCvtF32UByteNCombine()
9940 MVT::f32, Srl); in performCvtF32UByteNCombine()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 355 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
356 if (Srl.getOpcode() == ISD::SRL) { in isExtractHiElt()
357 if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) { in isExtractHiElt()
359 Out = stripBitcast(Srl.getOperand(0)); in isExtractHiElt()
2187 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
2188 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); in SelectS_BFE()
2199 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
|
| D | SIISelLowering.cpp | 10146 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
10148 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine()
10150 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, EltVT.changeTypeToInteger(), Srl); in performExtractVectorEltCombine()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 384 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
386 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) || in PreprocessISelDAG()
405 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG()
406 Srl.getOperand(0), in PreprocessISelDAG()
407 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl), in PreprocessISelDAG()
410 Srl, in PreprocessISelDAG()
411 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
413 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 1260 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
1261 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1)); in SelectS_BFE()
1272 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 421 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
423 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) || in PreprocessISelDAG()
442 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG()
443 Srl.getOperand(0), in PreprocessISelDAG()
444 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl), in PreprocessISelDAG()
447 Srl, in PreprocessISelDAG()
448 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
450 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 441 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
443 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) || in PreprocessISelDAG()
462 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG()
463 Srl.getOperand(0), in PreprocessISelDAG()
464 CurDAG->getConstant(Srl_imm + TZ, SDLoc(Srl), in PreprocessISelDAG()
467 Srl, in PreprocessISelDAG()
468 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
470 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstMIPS32.h | 269 Srl, enumerator
1274 using InstMIPS32Srl = InstMIPS32Imm16<InstMIPS32::Srl>;
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 936 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local
937 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract()
947 insertDAGNode(DAG, N, Srl); in foldMaskAndShiftToExtract()
|
| D | X86ISelLowering.cpp | 14907 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, in ConvertCmpIfNecessary() local
14909 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); in ConvertCmpIfNecessary()
20990 SDValue Srl = in LowerVectorCTPOPBitmath() local
20992 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55))); in LowerVectorCTPOPBitmath()
20997 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2)); in LowerVectorCTPOPBitmath()
20998 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33))); in LowerVectorCTPOPBitmath()
21002 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4)); in LowerVectorCTPOPBitmath()
21003 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl); in LowerVectorCTPOPBitmath()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1649 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local
1650 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract()
1660 insertDAGNode(DAG, N, Srl); in foldMaskAndShiftToExtract()
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| D | X86ISelLowering.cpp | 20914 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, in ConvertCmpIfNecessary() local
20916 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl); in ConvertCmpIfNecessary()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3840 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
3841 AddToWorklist(Srl.getNode()); in visitSDIVLike()
3842 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl); in visitSDIVLike()
5115 SDValue Srl = Not.getOperand(0); in combineShiftAnd1ToBitTest() local
5116 if (Srl.getOpcode() == ISD::TRUNCATE) in combineShiftAnd1ToBitTest()
5117 Srl = Srl.getOperand(0); in combineShiftAnd1ToBitTest()
5120 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() || in combineShiftAnd1ToBitTest()
5121 !isa<ConstantSDNode>(Srl.getOperand(1))) in combineShiftAnd1ToBitTest()
5127 const APInt &ShiftAmt = Srl.getConstantOperandAPInt(1); in combineShiftAnd1ToBitTest()
5135 SDValue X = DAG.getZExtOrTrunc(Srl.getOperand(0), DL, VT); in combineShiftAnd1ToBitTest()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 4116 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
4117 AddToWorklist(Srl.getNode()); in visitSDIVLike()
4118 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl); in visitSDIVLike()
5400 SDValue Srl = Not.getOperand(0); in combineShiftAnd1ToBitTest() local
5401 if (Srl.getOpcode() == ISD::TRUNCATE) in combineShiftAnd1ToBitTest()
5402 Srl = Srl.getOperand(0); in combineShiftAnd1ToBitTest()
5405 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() || in combineShiftAnd1ToBitTest()
5406 !isa<ConstantSDNode>(Srl.getOperand(1))) in combineShiftAnd1ToBitTest()
5412 const APInt &ShiftAmt = Srl.getConstantOperandAPInt(1); in combineShiftAnd1ToBitTest()
5420 SDValue X = DAG.getZExtOrTrunc(Srl.getOperand(0), DL, VT); in combineShiftAnd1ToBitTest()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1829 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local
1830 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract()
1840 insertDAGNode(DAG, N, Srl); in foldMaskAndShiftToExtract()
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 5213 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); in lowerFPTOSI() local
5219 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); in lowerFPTOSI()
|