Searched refs:SubOp1 (Results 1 – 7 of 7) sorted by relevance
| /external/llvm-project/llvm/unittests/Transforms/Utils/ |
| D | SSAUpdaterBulkTest.cpp | 57 Value *SubOp1 = B.CreateSub(FirstArg, ConstantInt::get(I32Ty, 2)); in TEST() local
68 auto *I3 = cast<Instruction>(B.CreateAdd(SubOp1, SubOp2)); in TEST()
69 auto *I4 = cast<Instruction>(B.CreateSub(SubOp1, SubOp2)); in TEST()
82 Updater.AddAvailableValue(VarNum, TrueBB, SubOp1); in TEST()
99 EXPECT_EQ(UpdatePhiB->getIncomingValueForBlock(TrueBB), SubOp1); in TEST()
104 EXPECT_EQ(I4->getOperand(0), SubOp1); in TEST()
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| /external/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| D | AggressiveInstCombine.cpp | 316 Value *Root, *SubOp1; in tryToRecognizePopCount() local
318 if (match(AndOp0, m_Sub(m_Value(Root), m_Value(SubOp1))) && in tryToRecognizePopCount()
319 match(SubOp1, m_And(m_LShr(m_Specific(Root), m_SpecificInt(1)), in tryToRecognizePopCount()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/AggressiveInstCombine/ |
| D | AggressiveInstCombine.cpp | 301 Value *Root, *SubOp1; in tryToRecognizePopCount() local
303 if (match(AndOp0, m_Sub(m_Value(Root), m_Value(SubOp1))) && in tryToRecognizePopCount()
304 match(SubOp1, m_And(m_LShr(m_Specific(Root), m_SpecificInt(1)), in tryToRecognizePopCount()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 16729 SDValue SubOp1 = Sub.getOperand(1); in combineTRUNCATE() local
16731 (SubOp1.getOpcode() == ISD::ZERO_EXTEND)) { in combineTRUNCATE()
16733 SubOp1.getOperand(0), in combineTRUNCATE()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 28381 SDValue SubOp1 = DAG.getNode(ISD::XOR, DL, MaskVT, V, Mask); in combineLogicBlendIntoPBLENDV() local
28395 std::swap(SubOp1, SubOp2); in combineLogicBlendIntoPBLENDV()
28398 DAG.getNode(ISD::SUB, DL, MaskVT, SubOp1, SubOp2)); in combineLogicBlendIntoPBLENDV()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 37863 SDValue SubOp1 = DAG.getNode(ISD::XOR, DL, MaskVT, V, Mask); in combineLogicBlendIntoConditionalNegate() local
37877 std::swap(SubOp1, SubOp2); in combineLogicBlendIntoConditionalNegate()
37879 SDValue Res = DAG.getNode(ISD::SUB, DL, MaskVT, SubOp1, SubOp2); in combineLogicBlendIntoConditionalNegate()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 40596 SDValue SubOp1 = DAG.getNode(ISD::XOR, DL, MaskVT, V, Mask); in combineLogicBlendIntoConditionalNegate() local
40610 std::swap(SubOp1, SubOp2); in combineLogicBlendIntoConditionalNegate()
40612 SDValue Res = DAG.getNode(ISD::SUB, DL, MaskVT, SubOp1, SubOp2); in combineLogicBlendIntoConditionalNegate()
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