| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
42 if (!RC.hasSubClassEq(&SubRC)) in verify()
47 assert((getSize() >= SubRC.getSize() * 8) && in verify()
49 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
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| D | RegisterBankInfo.cpp | 141 const TargetRegisterClass *SubRC = TRI.getRegClass(SubRCId); in addRegBankCoverage() local
142 for (SuperRegClassIterator SuperRCIt(SubRC, &TRI); SuperRCIt.isValid(); in addRegBankCoverage()
152 DEBUG(dbgs() << TRI.getRegClassName(SubRC) << ", "); in addRegBankCoverage()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
47 if (!RC.hasSubClassEq(&SubRC)) in verify()
52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
54 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify() local
47 if (!RC.hasSubClassEq(&SubRC)) in verify()
52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
54 assert(covers(SubRC) && "Not all subclasses are covered"); in verify()
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 117 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
118 if (SubRC->isAllocatable()) in getAllocatableClass()
119 return SubRC; in getAllocatableClass()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 179 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
180 if (SubRC->isAllocatable()) in getAllocatableClass()
181 return SubRC; in getAllocatableClass()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 199 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass() local
200 if (SubRC->isAllocatable()) in getAllocatableClass()
201 return SubRC; in getAllocatableClass()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 958 CodeGenRegisterClass &SubRC = *I2; in computeSubClasses() local
959 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
961 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
965 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
2224 CodeGenRegisterClass *SubRC = in inferSubClassWithSubReg() local
2227 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
2269 CodeGenRegisterClass &SubRC = *I; in inferMatchingSuperRegClass() local
2270 if (SubRC.Artificial) in inferMatchingSuperRegClass()
2273 if (!TopoSigs.anyCommon(SubRC.getTopoSigs())) in inferMatchingSuperRegClass()
2278 if (SubRC.contains(SSPairs[i].second)) in inferMatchingSuperRegClass()
[all …]
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| D | CodeGenRegisters.h | 401 CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg() argument
402 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
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| D | RISCVCompressInstEmitter.cpp | 164 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType); in validateTypes() local
165 return RC.hasSubClass(&SubRC); in validateTypes()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 861 CodeGenRegisterClass &SubRC = *I2; in computeSubClasses() local
862 if (RC.SubClasses.test(SubRC.EnumValue)) in computeSubClasses()
864 if (!testSubClass(&RC, &SubRC)) in computeSubClasses()
868 RC.SubClasses |= SubRC.SubClasses; in computeSubClasses()
1938 CodeGenRegisterClass *SubRC = in inferSubClassWithSubReg() local
1941 RC->setSubClassWithSubReg(&SubIdx, SubRC); in inferSubClassWithSubReg()
1983 CodeGenRegisterClass &SubRC = *I; in inferMatchingSuperRegClass() local
1985 if (!TopoSigs.anyCommon(SubRC.getTopoSigs())) in inferMatchingSuperRegClass()
1990 if (SubRC.contains(SSPairs[i].second)) in inferMatchingSuperRegClass()
1999 SubRC.addSuperRegClass(&SubIdx, RC); in inferMatchingSuperRegClass()
[all …]
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| D | CodeGenRegisters.h | 354 CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg() argument
355 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 143 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
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| D | SIInstrInfo.h | 49 const TargetRegisterClass *SubRC) const;
55 const TargetRegisterClass *SubRC) const;
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| D | SIRegisterInfo.cpp | 832 const TargetRegisterClass *SubRC, in getPhysRegSubReg() argument
891 return SubRC->getRegister(Index + Channel); in getPhysRegSubReg()
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| D | SIInstrInfo.cpp | 1906 const TargetRegisterClass *SubRC) in buildExtractSubReg()
1910 unsigned SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg()
1939 const TargetRegisterClass *SubRC) const { in buildExtractSubRegOrImm()
1951 SubIdx, SubRC); in buildExtractSubRegOrImm()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.h | 81 const TargetRegisterClass &SubRC,
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| D | SIInstrInfo.h | 74 const TargetRegisterClass *SubRC) const;
80 const TargetRegisterClass *SubRC) const;
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| D | AMDGPUInstructionSelector.cpp | 205 const TargetRegisterClass &SubRC, in getSubOperand64() argument
210 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 311 const TargetRegisterClass *SubRC = TRI->getSubRegClass(RC, SubReg); in getPhysRegBank() local
313 if (TRI->getRegSizeInBits(*SubRC) > 32) in getPhysRegBank()
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| D | AMDGPUInstructionSelector.h | 88 const TargetRegisterClass &SubRC,
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| D | SIInstrInfo.h | 74 const TargetRegisterClass *SubRC) const;
80 const TargetRegisterClass *SubRC) const;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3481 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
3485 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
3491 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
3496 unsigned NewVR = MRI.createVirtualRegister(SubRC); in genAlternativeCodeSequence()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 4457 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
4461 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
4467 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
4472 Register NewVR = MRI.createVirtualRegister(SubRC); in genAlternativeCodeSequence()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 4833 const TargetRegisterClass *SubRC; in genAlternativeCodeSequence() local
4837 SubRC = &AArch64::GPR32spRegClass; in genAlternativeCodeSequence()
4843 SubRC = &AArch64::GPR64spRegClass; in genAlternativeCodeSequence()
4848 Register NewVR = MRI.createVirtualRegister(SubRC); in genAlternativeCodeSequence()
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