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Searched refs:SubRegIdx (Results 1 – 25 of 66) sorted by relevance

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/external/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
225 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
226 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
336 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
337 if (SubRegIdx == 0) in computeMainRangesFixFlags()
DRegisterPressure.cpp492 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
495 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
500 SubRegIdx = 0; in collectOperandLanes()
504 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
506 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
510 void pushRegLanes(unsigned Reg, unsigned SubRegIdx, in pushRegLanes() argument
513 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
514 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1192 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1193 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
DStackMaps.cpp145 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
146 if (SubRegIdx) in parseOperand()
147 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
DVirtRegMap.cpp340 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
341 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
DMachineVerifier.cpp1224 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1225 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1226 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
1325 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1326 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1327 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
/external/llvm-project/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
348 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
349 if (SubRegIdx == 0) in computeMainRangesFixFlags()
DRegisterPressure.cpp535 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
538 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
543 SubRegIdx = 0; in collectOperandLanes()
547 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
549 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
553 void pushRegLanes(Register Reg, unsigned SubRegIdx, in pushRegLanes() argument
556 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
557 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1235 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1236 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
DVirtRegMap.cpp363 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
364 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
365 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
DStackMaps.cpp234 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
235 if (SubRegIdx) in parseOperand()
236 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
227 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
348 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
349 if (SubRegIdx == 0) in computeMainRangesFixFlags()
DRegisterPressure.cpp534 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
537 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
542 SubRegIdx = 0; in collectOperandLanes()
546 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
548 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
552 void pushRegLanes(unsigned Reg, unsigned SubRegIdx, in pushRegLanes() argument
555 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
556 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1233 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1234 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
DVirtRegMap.cpp363 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
364 assert(SubRegIdx != 0 && LI.hasSubRanges()); in readsUndefSubreg()
365 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
DStackMaps.cpp159 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
160 if (SubRegIdx) in parseOperand()
161 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
DRegAllocFast.cpp768 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef() local
769 if (SubRegIdx != 0) { in allocVirtRegUndef()
770 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrPatternsVec.td18 …elem32<ValueType v32, ValueType s32, SDPatternOperator ImmOp, SDNodeXForm ImmCast, int SubRegIdx> {
26 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, SubRegIdx),
DVEInstrInfo.cpp330 const unsigned *SubRegIdx, in copyPhysSubRegs() argument
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); in copyPhysSubRegs()
384 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg() local
387 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
/external/llvm/lib/Target/X86/
DX86FixupBWInsts.cpp190 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
196 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
202 if (SubRegIdx == X86::sub_8bit) { in getSuperRegDestIfDead()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupBWInsts.cpp195 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
201 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
209 if (SubRegIdx != X86::sub_8bit) in getSuperRegDestIfDead()
DX86FlagsCopyLowering.cpp1002 int SubRegIdx[] = {X86::NoSubRegister, X86::sub_8bit, X86::sub_16bit, in rewriteSetCarryExtended() local
1025 .addImm(SubRegIdx[OrigRegSize]); in rewriteSetCarryExtended()
1034 .addReg(Reg, 0, SubRegIdx[TargetRegSize]); in rewriteSetCarryExtended()
/external/llvm-project/llvm/lib/Target/X86/
DX86FixupBWInsts.cpp194 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
200 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
208 if (SubRegIdx != X86::sub_8bit) in getSuperRegDestIfDead()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp1198 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeSBufferLoadImmPair() local
1199 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeSBufferLoadImmPair()
1200 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeSBufferLoadImmPair()
1260 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeBufferLoadPair() local
1261 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeBufferLoadPair()
1262 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeBufferLoadPair()
1327 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferLoadPair() local
1328 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferLoadPair()
1329 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferLoadPair()
1357 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferStorePair() local
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp1258 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeSBufferLoadImmPair() local
1259 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeSBufferLoadImmPair()
1260 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeSBufferLoadImmPair()
1321 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeBufferLoadPair() local
1322 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeBufferLoadPair()
1323 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeBufferLoadPair()
1389 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferLoadPair() local
1390 const unsigned SubRegIdx0 = std::get<0>(SubRegIdx); in mergeTBufferLoadPair()
1391 const unsigned SubRegIdx1 = std::get<1>(SubRegIdx); in mergeTBufferLoadPair()
1420 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferStorePair() local
[all …]
/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.cpp476 CodeGenSubRegIndex *SubRegIdx; in computeSecondarySubRegs() local
478 std::tie(SubRegIdx, SubReg) = SubRegQueue.front(); in computeSecondarySubRegs()
496 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
498 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs() local
499 if (SubRegIdx->ConcatenationOf.empty()) { in computeSecondarySubRegs()
500 Parts.push_back(SubRegIdx); in computeSecondarySubRegs()
502 for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf) in computeSecondarySubRegs()
/external/llvm-project/llvm/test/TableGen/
DGlobalISelEmitterSubreg.td131 // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // src
188 // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h816 int64_t SubRegIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
819 0, SubRegIdx); in executeMatchTable()
823 << OpIdx << ", " << SubRegIdx << ")\n"); in executeMatchTable()

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