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Searched refs:SuperRC (Results 1 – 25 of 36) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp982 const TargetRegisterClass *SuperRC = in mergeRead2Pair() local
984 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1124 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1126 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1177 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSBufferLoadImmPair() local
1179 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSBufferLoadImmPair()
1228 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local
1231 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
1290 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferLoadPair() local
1293 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair()
[all …]
DSIInstrInfo.h72 const TargetRegisterClass *SuperRC,
78 const TargetRegisterClass *SuperRC,
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp1039 const TargetRegisterClass *SuperRC = in mergeRead2Pair() local
1041 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1183 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1185 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1237 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSBufferLoadImmPair() local
1239 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSBufferLoadImmPair()
1289 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local
1292 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
1352 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferLoadPair() local
1355 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair()
[all …]
DSIInstrInfo.h72 const TargetRegisterClass *SuperRC,
78 const TargetRegisterClass *SuperRC,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp629 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
632 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
640 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
642 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
736 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
737 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
DMachineCopyPropagation.cpp435 const TargetRegisterClass *SuperRC = UseDstRC; in isForwardableRegClassCopy() local
437 SuperRC; SuperRC = *SuperRCI++) in isForwardableRegClassCopy()
438 if (SuperRC->contains(CopySrcReg)) in isForwardableRegClassCopy()
DRegAllocGreedy.cpp2065 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
2068 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
2071 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
2105 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
2107 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
2116 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
DTargetLoweringBase.cpp1128 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1130 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1132 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1134 BestRC = SuperRC; in findRepresentativeClass()
/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp611 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
614 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
622 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
624 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
717 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
718 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
DRegAllocGreedy.cpp1560 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1563 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1566 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1599 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1601 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1610 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
DTargetLoweringBase.cpp1277 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1279 if (SuperRC->getSize() <= BestRC->getSize()) in findRepresentativeClass()
1281 if (!isLegalRC(SuperRC)) in findRepresentativeClass()
1283 BestRC = SuperRC; in findRepresentativeClass()
DMachineVerifier.cpp1031 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
1033 if (!SuperRC) { in visitMachineOperand()
1037 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/external/llvm-project/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp624 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
627 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
635 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
637 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
731 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
732 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
DMachineCopyPropagation.cpp436 const TargetRegisterClass *SuperRC = UseDstRC; in isForwardableRegClassCopy() local
438 SuperRC; SuperRC = *SuperRCI++) in isForwardableRegClassCopy()
439 if (SuperRC->contains(CopySrcReg)) in isForwardableRegClassCopy()
DRegAllocGreedy.cpp2054 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
2057 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
2060 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
2094 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
2096 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
2105 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, in tryInstructionSplit()
DTargetLoweringBase.cpp1274 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1276 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1278 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1280 BestRC = SuperRC; in findRepresentativeClass()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp338 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
339 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
DHexagonCopyToCombine.cpp594 const TargetRegisterClass *SuperRC = nullptr; in combine() local
596 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
600 SuperRC = &Hexagon::HvxWRRegClass; in combine()
606 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp331 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
332 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
DHexagonCopyToCombine.cpp588 const TargetRegisterClass *SuperRC = nullptr; in combine() local
590 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
594 SuperRC = &Hexagon::HvxWRRegClass; in combine()
600 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
/external/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp229 const TargetRegisterClass *SuperRC in mergeRead2Pair() local
231 unsigned DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
DSIInstrInfo.h47 const TargetRegisterClass *SuperRC,
53 const TargetRegisterClass *SuperRC,
DSILowerControlFlow.cpp604 const TargetRegisterClass *SuperRC = TRI->getPhysRegClass(VecReg); in computeIndirectRegAndOffset() local
606 int NumElts = SuperRC->getSize() / RC->getSize(); in computeIndirectRegAndOffset()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h365 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.h412 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
413 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()

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