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Searched refs:T1_ADDRESS_REG_NR_SHIFT (Results 1 – 14 of 14) sorted by relevance

/external/mesa3d/src/gallium/drivers/i915/
Di915_debug_fp.c304 (program[1] >> T1_ADDRESS_REG_NR_SHIFT) & REG_NR_MASK); in print_tex_op()
317 (program[1] >> T1_ADDRESS_REG_NR_SHIFT) & REG_NR_MASK); in print_texkil_op()
Di915_fpc.h166 #define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \
Di915_reg.h660 #define T1_ADDRESS_REG_NR_SHIFT 17 macro
/external/igt-gpu-tools/lib/
Di915_3d.h195 #define T1_ADDRESS_REG_NR_SHIFT 17 macro
374 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
385 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
Drendercopy_i915.c203 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT)); in gen3_render_copyfunc()
Di915_reg.h644 #define T1_ADDRESS_REG_NR_SHIFT 17 macro
/external/mesa3d/src/mesa/drivers/dri/i915/
Di915_debug_fp.c289 (program[1] >> T1_ADDRESS_REG_NR_SHIFT) & REG_NR_MASK); in print_tex_op()
Di915_reg.h532 #define T1_ADDRESS_REG_NR_SHIFT 17 macro
Di915_program.c54 #define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \
/external/igt-gpu-tools/tests/i915/
Dgen3_render_linear_blits.c216 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT)); in copy()
Dgen3_render_tiledy_blits.c216 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT)); in copy()
Dgen3_render_tiledx_blits.c216 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT)); in copy()
Dgen3_render_mixed_blits.c229 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT)); in copy()
Dgen3_mixed_blits.c242 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT)); in render_copy()