Searched refs:TEGRA_CLK_RST_CTL_CLK_SRC_SE (Results 1 – 2 of 2) sorted by relevance
157 #define TEGRA_CLK_RST_CTL_CLK_SRC_SE U(0x42C) macro
934 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE, in tegra_se_enable_clocks()