Searched refs:TEGRA_FLOWCTRL_BASE (Results 1 – 4 of 4) sorted by relevance
27 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR),28 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR),29 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8),30 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16)34 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS),35 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS),36 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8),37 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16)41 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL),42 (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4),[all …]
75 return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); in tegra_fc_read_32()80 mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); in tegra_fc_write_32()
63 #define TEGRA_FLOWCTRL_BASE U(0x60007000) macro
170 #define TEGRA_FLOWCTRL_BASE U(0x60007000) macro