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Searched refs:TEGRA_PMC_BASE (Results 1 – 9 of 9) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/
Dplat_sip_calls.c83 val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2)); in plat_sip_handler()
86 mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3); in plat_sip_handler()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
Dpmc.h57 return mmio_read_32(TEGRA_PMC_BASE + off); in tegra_pmc_read_32()
62 mmio_write_32(TEGRA_PMC_BASE + off, val); in tegra_pmc_write_32()
/external/arm-trusted-firmware/plat/nvidia/tegra/drivers/pmc/
Dpmc.c133 mmio_write_32((TEGRA_PMC_BASE + PMC_IO_DPD_SAMPLE), 0x0); in tegra_pmc_resume()
136 mmio_write_32((TEGRA_PMC_BASE + PMC_DPD_ENABLE_0), 0x0); in tegra_pmc_resume()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t132/
Dtegra_def.h93 #define TEGRA_PMC_BASE U(0x7000E400) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t210/
Dtegra_def.h219 #define TEGRA_PMC_BASE U(0x7000E400) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t186/
Dtegra_def.h256 #define TEGRA_PMC_BASE U(0x0C360000) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t194/
Dtegra_def.h213 #define TEGRA_PMC_BASE U(0x0C360000) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_setup.c99 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/drivers/se/
Dsecurity_engine.c872 mmio_write_32((uint64_t)TEGRA_PMC_BASE + PMC_SCRATCH43_REG_OFFSET, in tegra_se_context_save_sw()
876 mmio_write_32((uint64_t)TEGRA_PMC_BASE + PMC_SECURE_SCRATCH116_OFFSET, in tegra_se_context_save_sw()