Searched refs:TGSI_OPCODE_AND (Results 1 – 16 of 16) sorted by relevance
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 129 { 1, 2, 0, 0, 0, 0, COMP, "AND", TGSI_OPCODE_AND },
364 case TGSI_OPCODE_AND: in tgsi_opcode_infer_type()
|
| D | tgsi_util.c | 214 case TGSI_OPCODE_AND: in tgsi_util_get_inst_usage_mask()
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 131 case TGSI_OPCODE_AND: in tgsi_opcode_infer_type()
|
| D | tgsi_exec.c | 5682 case TGSI_OPCODE_AND: in exec_instruction()
|
| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 439 TGSI_OPCODE_AND = 89, enumerator
|
| /external/virglrenderer/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 422 #define TGSI_OPCODE_AND 89 macro
|
| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi.cpp | 1636 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2); in visit_expression()
1642 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2); in visit_expression()
1646 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2); in visit_expression()
1651 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2); in visit_expression()
1789 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]); in visit_expression()
1826 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], in visit_expression()
1845 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], in visit_expression()
1972 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]); in visit_expression()
2269 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1)); in visit_expression()
2295 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], in visit_expression()
[all …]
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_aos.c | 797 case TGSI_OPCODE_AND: in lp_emit_instruction_aos()
|
| D | lp_bld_tgsi_action.c | 2536 bld_base->op_actions[TGSI_OPCODE_AND].emit = and_emit_cpu; in lp_set_default_actions_cpu()
|
| /external/mesa3d/src/gallium/auxiliary/nir/ |
| D | nir_to_tgsi.c | 652 [nir_op_iand] = { TGSI_OPCODE_AND, TGSI_OPCODE_AND }, in ntt_emit_alu()
|
| D | tgsi_to_nir.c | 1865 [TGSI_OPCODE_AND] = nir_op_iand,
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 518 case TGSI_OPCODE_AND: in inferSrcType()
3138 case TGSI_OPCODE_AND: in handleInstruction()
|
| /external/mesa3d/src/gallium/drivers/svga/ |
| D | svga_tgsi_insn.c | 2883 case TGSI_OPCODE_AND: in svga_emit_instruction()
|
| D | svga_tgsi_vgpu10.c | 839 case TGSI_OPCODE_AND: in translate_opcode()
9227 case TGSI_OPCODE_AND: in emit_vgpu10_instruction()
|
| /external/virglrenderer/src/ |
| D | vrend_shader.c | 4296 (inst->Instruction.Opcode == TGSI_OPCODE_AND) && in get_source_info()
5043 case TGSI_OPCODE_AND: in iter_instruction()
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 11762 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
11959 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
12185 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
|