Searched refs:TGSI_OPCODE_ARL (Results 1 – 18 of 18) sorted by relevance
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 156 case TGSI_OPCODE_ARL: in tgsi_opcode_infer_type()
292 case TGSI_OPCODE_ARL: in tgsi_opcode_infer_src_type()
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| D | tgsi_exec.c | 5245 case TGSI_OPCODE_ARL: in exec_instruction()
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 40 { 1, 1, 0, 0, 0, 0, COMP, "ARL", TGSI_OPCODE_ARL },
389 case TGSI_OPCODE_ARL: in tgsi_opcode_infer_type()
507 case TGSI_OPCODE_ARL: in tgsi_opcode_infer_src_type()
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| D | tgsi_util.c | 183 case TGSI_OPCODE_ARL: in tgsi_util_get_inst_usage_mask()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 351 TGSI_OPCODE_ARL = 0, enumerator
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| /external/virglrenderer/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 337 #define TGSI_OPCODE_ARL 0 macro
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| /external/mesa3d/src/gallium/drivers/r300/ |
| D | r300_tgsi_to_rc.c | 36 case TGSI_OPCODE_ARL: return RC_OPCODE_ARL; in translate_opcode()
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| /external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| D | nvfx_vertprog.c | 538 finst->Instruction.Opcode != TGSI_OPCODE_ARL) in nvfx_vertprog_parse_instruction()
544 assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL); in nvfx_vertprog_parse_instruction()
556 case TGSI_OPCODE_ARL: in nvfx_vertprog_parse_instruction()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_mesa_to_tgsi.c | 456 return TGSI_OPCODE_ARL; in translate_opcode()
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| D | st_glsl_to_tgsi.cpp | 877 enum tgsi_opcode op = TGSI_OPCODE_ARL; in emit_arl()
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_aos.c | 457 case TGSI_OPCODE_ARL: in lp_emit_instruction_aos()
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| D | lp_bld_tgsi_action.c | 2537 bld_base->op_actions[TGSI_OPCODE_ARL].emit = arl_emit_cpu; in lp_set_default_actions_cpu()
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| /external/mesa3d/src/gallium/auxiliary/nir/ |
| D | tgsi_to_nir.c | 1791 [TGSI_OPCODE_ARL] = 0,
2028 case TGSI_OPCODE_ARL: in ttn_emit_instruction()
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| /external/mesa3d/src/gallium/drivers/svga/ |
| D | svga_tgsi_insn.c | 2770 case TGSI_OPCODE_ARL: in svga_emit_instruction()
3619 TGSI_OPCODE_ARL) { in pre_parse_tokens()
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| D | svga_tgsi_vgpu10.c | 6339 if (inst->Instruction.Opcode == TGSI_OPCODE_ARL) in emit_arl_uarl()
9323 case TGSI_OPCODE_ARL: in emit_vgpu10_instruction()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 10202 case TGSI_OPCODE_ARL: in tgsi_eg_arl()
10244 case TGSI_OPCODE_ARL: in tgsi_r600_arl()
11671 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
11872 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
12098 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 3206 case TGSI_OPCODE_ARL: in handleInstruction()
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| /external/virglrenderer/src/ |
| D | vrend_shader.c | 5186 case TGSI_OPCODE_ARL: in iter_instruction()
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