Searched refs:TGSI_OPCODE_DMIN (Results 1 – 11 of 11) sorted by relevance
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 244 { 1, 2, 0, 0, 0, 0, COMP, "DMIN", TGSI_OPCODE_DMIN },
432 case TGSI_OPCODE_DMIN: in tgsi_opcode_infer_type()
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 199 case TGSI_OPCODE_DMIN: in tgsi_opcode_infer_type()
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| D | tgsi_exec.c | 6077 case TGSI_OPCODE_DMIN: in exec_instruction()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 566 TGSI_OPCODE_DMIN = 202 /* SM5 */, enumerator
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| /external/virglrenderer/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 548 #define TGSI_OPCODE_DMIN 202 /* SM5 */ macro
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| /external/mesa3d/src/gallium/drivers/svga/ |
| D | svga_tgsi_vgpu10.c | 931 case TGSI_OPCODE_DMIN: in translate_opcode()
8547 case TGSI_OPCODE_DMIN: in opcode_has_dbl_dst()
8572 case TGSI_OPCODE_DMIN: in opcode_has_dbl_src()
8619 case TGSI_OPCODE_DMIN: in check_double_dst_writemask()
9286 case TGSI_OPCODE_DMIN: in emit_vgpu10_instruction()
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 587 case TGSI_OPCODE_DMIN: in inferSrcType()
4045 case TGSI_OPCODE_DMIN: in handleInstruction()
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| /external/mesa3d/src/gallium/auxiliary/nir/ |
| D | nir_to_tgsi.c | 656 [nir_op_fmin] = { TGSI_OPCODE_MIN, TGSI_OPCODE_DMIN }, in ntt_emit_alu()
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_action.c | 1211 bld_base->op_actions[TGSI_OPCODE_DMIN].emit = fmin_emit; in lp_set_default_actions()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 12073 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
12299 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
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| /external/virglrenderer/src/ |
| D | vrend_shader.c | 4881 case TGSI_OPCODE_DMIN: in iter_instruction()
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