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Searched refs:TGSI_OPCODE_ISHR (Results 1 – 16 of 16) sorted by relevance

/external/virglrenderer/src/gallium/auxiliary/tgsi/
Dtgsi_info.c165 { 1, 2, 0, 0, 0, 0, COMP, "ISHR", TGSI_OPCODE_ISHR },
402 case TGSI_OPCODE_ISHR: in tgsi_opcode_infer_type()
Dtgsi_util.c227 case TGSI_OPCODE_ISHR: in tgsi_util_get_inst_usage_mask()
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_info.c169 case TGSI_OPCODE_ISHR: in tgsi_opcode_infer_type()
Dtgsi_exec.c5842 case TGSI_OPCODE_ISHR: in exec_instruction()
/external/mesa3d/src/gallium/include/pipe/
Dp_shader_tokens.h475 TGSI_OPCODE_ISHR = 125, enumerator
/external/virglrenderer/src/gallium/include/pipe/
Dp_shader_tokens.h458 #define TGSI_OPCODE_ISHR 125 macro
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi_aos.c792 case TGSI_OPCODE_ISHR: in lp_emit_instruction_aos()
Dlp_bld_tgsi_action.c2558 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = ishr_emit_cpu; in lp_set_default_actions_cpu()
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_from_tgsi.cpp566 case TGSI_OPCODE_ISHR: in inferSrcType()
3156 case TGSI_OPCODE_ISHR: in handleInstruction()
/external/mesa3d/src/gallium/auxiliary/nir/
Dnir_to_tgsi.c645 [nir_op_ishr] = { TGSI_OPCODE_ISHR, TGSI_OPCODE_I64SHR }, in ntt_emit_alu()
Dtgsi_to_nir.c1898 [TGSI_OPCODE_ISHR] = nir_op_ishr,
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_insn.c2888 case TGSI_OPCODE_ISHR: in svga_emit_instruction()
Dsvga_tgsi_vgpu10.c875 case TGSI_OPCODE_ISHR: in translate_opcode()
9255 case TGSI_OPCODE_ISHR: in emit_vgpu10_instruction()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c11798 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
11995 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
12221 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
/external/mesa3d/src/mesa/state_tracker/
Dst_glsl_to_tgsi.cpp1952 ? TGSI_OPCODE_SHL : TGSI_OPCODE_ISHR; in visit_expression()
/external/virglrenderer/src/
Dvrend_shader.c5026 case TGSI_OPCODE_ISHR: in iter_instruction()