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Searched refs:TGSI_WRITEMASK_XYZW (Results 1 – 25 of 42) sorted by relevance

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/external/virglrenderer/src/gallium/auxiliary/tgsi/
Dtgsi_util.c274 read_mask = TGSI_WRITEMASK_XYZW; in tgsi_util_get_inst_usage_mask()
278 read_mask = src_idx == 0 ? TGSI_WRITEMASK_XYZ : TGSI_WRITEMASK_XYZW; in tgsi_util_get_inst_usage_mask()
314 read_mask = TGSI_WRITEMASK_XYZW; in tgsi_util_get_inst_usage_mask()
326 read_mask = TGSI_WRITEMASK_XYZW; in tgsi_util_get_inst_usage_mask()
332 read_mask = TGSI_WRITEMASK_XYZW; in tgsi_util_get_inst_usage_mask()
Dtgsi_ureg.c264 dst.WriteMask = TGSI_WRITEMASK_XYZW; in ureg_dst_register()
410 return ureg_DECL_output_masked(ureg, name, index, TGSI_WRITEMASK_XYZW); in ureg_DECL_output()
1224 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; /* FIXME! */ in emit_decl_fs()
1255 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_temps()
1280 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_range()
1301 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_range2D()
1388 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_atomic_2d()
1437 TGSI_WRITEMASK_XYZW); in emit_decls()
1447 TGSI_WRITEMASK_XYZW); in emit_decls()
Dtgsi_build.c106 declaration.UsageMask = TGSI_WRITEMASK_XYZW; in tgsi_default_declaration()
967 dst_register.WriteMask = TGSI_WRITEMASK_XYZW; in tgsi_default_dst_register()
989 assert( mask <= TGSI_WRITEMASK_XYZW ); in tgsi_build_dst_register()
Dtgsi_scan.c528 dst->Register.WriteMask != TGSI_WRITEMASK_XYZW) in tgsi_is_passthrough_shader()
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_lowering.c287 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_lrp()
292 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW); in transform_lrp()
304 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW); in transform_lrp()
335 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_frc()
340 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW); in transform_frc()
349 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW); in transform_frc()
381 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_pow()
405 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW); in transform_pow()
832 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) { in transform_dotp()
883 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW); in transform_dotp()
[all …]
Dtgsi_util.c250 read_mask = TGSI_WRITEMASK_XYZW; in tgsi_util_get_inst_usage_mask()
374 read_mask = TGSI_WRITEMASK_XYZW; in tgsi_util_get_inst_usage_mask()
395 read_mask = TGSI_WRITEMASK_XYZW; in tgsi_util_get_inst_usage_mask()
415 read_mask = TGSI_WRITEMASK_XYZW; /* assume all channels are read */ in tgsi_util_get_inst_usage_mask()
Dtgsi_point_sprite.c257 ts->point_size_tmp, TGSI_WRITEMASK_XYZW); in psprite_prolog()
286 TGSI_WRITEMASK_XYZW, in psprite_emit_vertex_inst()
348 TGSI_WRITEMASK_XYZW, in psprite_emit_vertex_inst()
358 TGSI_WRITEMASK_XYZW); in psprite_emit_vertex_inst()
384 dstReg, TGSI_WRITEMASK_XYZW); in psprite_emit_vertex_inst()
Dtgsi_ureg.c301 assert(usage_mask <= TGSI_WRITEMASK_XYZW); in ureg_DECL_fs_input_cyl_centroid_layout()
352 ureg->nr_input_regs, TGSI_WRITEMASK_XYZW, array_id, array_size); in ureg_DECL_fs_input_cyl_centroid()
499 return ureg_DECL_output_masked(ureg, name, index, TGSI_WRITEMASK_XYZW, in ureg_DECL_output()
511 TGSI_WRITEMASK_XYZW, in ureg_DECL_output_array()
1565 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_atomic_2d()
1639 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_temps()
1664 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_range()
1685 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_range2D()
1711 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_sampler_view()
1739 out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW; in emit_decl_image()
[all …]
Dtgsi_vpos.c71 0, TGSI_WRITEMASK_XYZW); in write_vpos_prolog()
Dtgsi_emulate.c90 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in passthrough_edgeflag()
Dtgsi_build.c106 declaration.UsageMask = TGSI_WRITEMASK_XYZW; in tgsi_default_declaration()
983 dst_register.WriteMask = TGSI_WRITEMASK_XYZW; in tgsi_default_dst_register()
1005 assert( mask <= TGSI_WRITEMASK_XYZW ); in tgsi_build_dst_register()
Dtgsi_ureg.h1037 dst.WriteMask = TGSI_WRITEMASK_XYZW; in ureg_dst_array_register()
1069 dst.WriteMask = TGSI_WRITEMASK_XYZW; in ureg_dst()
Dtgsi_transform.h197 decl.Declaration.UsageMask = TGSI_WRITEMASK_XYZW; in tgsi_transform_sampler_view_decl()
/external/mesa3d/src/mesa/state_tracker/
Dst_atifs_to_tgsi.c719 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_instr()
735 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_instr()
746 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_instr()
761 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_instr()
772 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_instr()
783 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_instr()
796 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_instr()
807 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_instr()
Dst_tgsi_lower_depth_clamp.c129 TGSI_WRITEMASK_XYZW, in epilog_last_vertex_stage()
245 TGSI_WRITEMASK_XYZW, in prolog_fs()
Dst_cb_drawpixels_shader.c152 TGSI_WRITEMASK_XYZW, in transform_instr()
Dst_tgsi_lower_yuv.c239 ctx->tmp[i].dst.Register.WriteMask = TGSI_WRITEMASK_XYZW; in emit_decls()
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi_info.c142 readmask = TGSI_WRITEMASK_XYZW; in analyse_tex()
149 readmask = TGSI_WRITEMASK_XYZW; in analyse_tex()
235 readmask = TGSI_WRITEMASK_XYZW; in analyse_sample()
/external/mesa3d/src/gallium/drivers/r300/
Dr300_vs_draw.c253 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_inst()
265 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW; in transform_inst()
/external/mesa3d/src/gallium/auxiliary/util/
Du_pstipple.c345 TGSI_WRITEMASK_XYZW, in pstip_transform_prolog()
Du_simple_shaders.c323 if (writemask != TGSI_WRITEMASK_XYZW) { in util_make_fragment_tex_shader_writemask()
375 TGSI_WRITEMASK_XYZW, in util_make_fragment_tex_shader()
/external/mesa3d/src/gallium/include/pipe/
Dp_shader_tokens.h98 #define TGSI_WRITEMASK_XYZW 0x0F macro
/external/virglrenderer/src/gallium/include/pipe/
Dp_shader_tokens.h103 #define TGSI_WRITEMASK_XYZW 0x0F macro
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shaderlib_tgsi.c735 struct ureg_dst coord = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_XYZW); in si_create_fmask_expand_cs()
/external/mesa3d/src/gallium/frontends/nine/
Dnine_ff.c667 tmp.WriteMask = TGSI_WRITEMASK_XYZW; in nine_ff_build_vs()
693 tmp.WriteMask = TGSI_WRITEMASK_XYZW; in nine_ff_build_vs()
706 writemask = TGSI_WRITEMASK_XYZW; in nine_ff_build_vs()
1481 dst.WriteMask = TGSI_WRITEMASK_XYZW; in nine_ff_build_ps()
1488 if (dst.WriteMask != TGSI_WRITEMASK_XYZW) { in nine_ff_build_ps()

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