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Searched refs:TReg (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/CodeGen/
DEarlyIfConversion.cpp112 unsigned TReg, FReg; member
117 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {} in PHIInfo()
415 PI.TReg = PI.PHI->getOperand(i).getReg(); in canConvertIf()
419 assert(TargetRegisterInfo::isVirtualRegister(PI.TReg) && "Bad PHI"); in canConvertIf()
423 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg, in canConvertIf()
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); in replacePHIInstrs()
485 if (PI.TReg == PI.FReg) { in rewritePHIOperands()
488 DstReg = PI.TReg; in rewritePHIOperands()
493 DstReg, Cond, PI.TReg, PI.FReg); in rewritePHIOperands()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DEarlyIfConversion.cpp113 unsigned TReg, FReg; member
118 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {} in PHIInfo()
515 PI.TReg = PI.PHI->getOperand(i).getReg(); in canConvertIf()
519 assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI"); in canConvertIf()
523 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg, in canConvertIf()
571 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); in replacePHIInstrs()
592 if (PI.TReg == PI.FReg) { in rewritePHIOperands()
595 DstReg = PI.TReg; in rewritePHIOperands()
600 DstReg, Cond, PI.TReg, PI.FReg); in rewritePHIOperands()
/external/llvm-project/llvm/lib/CodeGen/
DEarlyIfConversion.cpp114 unsigned TReg, FReg; member
119 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {} in PHIInfo()
518 PI.TReg = PI.PHI->getOperand(i).getReg(); in canConvertIf()
522 assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI"); in canConvertIf()
527 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles, in canConvertIf()
575 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); in replacePHIInstrs()
596 if (PI.TReg == PI.FReg) { in rewritePHIOperands()
599 DstReg = PI.TReg; in rewritePHIOperands()
604 DstReg, Cond, PI.TReg, PI.FReg); in rewritePHIOperands()
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringMIPS32.cpp2140 Variable *TReg = Target->makeReg(IceType_i32, Target->getReservedTmpReg()); in legalizeImmediate() local
2143 Target->_lui(TReg, Target->Ctx->getConstantInt32(UpperBits)); in legalizeImmediate()
2144 Target->_ori(Reg, TReg, LowerBits); in legalizeImmediate()
3050 auto *TReg = makeReg(IceType_i32); in lowerAssign() local
3051 _mov(TReg, SCont); in lowerAssign()
3052 _mov(DCont, TReg); in lowerAssign()
3900 Variable *TReg = makeReg(DestTy); in lowerExtractElement() local
3930 _srl(TReg, SrcE, 8); in lowerExtractElement()
3931 _andi(TDest, TReg, 0xff); in lowerExtractElement()
3934 _srl(TReg, SrcE, 16); in lowerExtractElement()
[all …]
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp3388 unsigned TReg = Inst.getOperand(2).getReg(); in expandRotation() local
3403 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
3409 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
3435 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
3437 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
3517 unsigned TReg = Inst.getOperand(2).getReg(); in expandDRotation() local
3532 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
3538 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
3564 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
3566 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp1360 unsigned TReg = MI->getOperand(0).getReg(); in EmitInstruction() local
1363 if (ThumbIndirectPads[i].first == TReg) { in EmitInstruction()
1371 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym)); in EmitInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp588 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); in insertSelect() local
590 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
592 TrueReg = TReg; in insertSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp1335 Register TReg = MI->getOperand(0).getReg(); in EmitInstruction() local
1338 if (TIP.first == TReg) { in EmitInstruction()
1346 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym)); in EmitInstruction()
/external/llvm-project/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp1380 Register TReg = MI->getOperand(0).getReg(); in emitInstruction() local
1383 if (TIP.first == TReg) { in emitInstruction()
1391 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym)); in emitInstruction()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp589 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); in insertSelect() local
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
593 TrueReg = TReg; in insertSelect()
/external/llvm-project/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp4862 unsigned TReg = Inst.getOperand(2).getReg(); in expandRotation() local
4876 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4907 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4987 unsigned TReg = Inst.getOperand(2).getReg(); in expandDRotation() local
5001 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
5007 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
5032 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
5034 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp4752 unsigned TReg = Inst.getOperand(2).getReg(); in expandRotation() local
4766 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4772 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4797 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandRotation()
4799 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4877 unsigned TReg = Inst.getOperand(2).getReg(); in expandDRotation() local
4891 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
4897 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
4922 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI); in expandDRotation()
4924 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandDRotation()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp4646 SDValue TReg = getI8Imm(TIndex, dl); in Select() local
4655 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, TReg, Chain }; in Select()
4658 SDValue Ops[] = { TReg, Base, Scale, Index, Disp, Segment, Chain }; in Select()
DX86ISelLowering.cpp33443 Register TReg = MRI->createVirtualRegister(&X86::GR64RegClass); in EmitSjLjDispatchBlock() local
33455 BuildMI(DispContBB, DL, TII->get(X86::ADD64rr), TReg) in EmitSjLjDispatchBlock()
33459 BuildMI(DispContBB, DL, TII->get(X86::JMP64r)).addReg(TReg); in EmitSjLjDispatchBlock()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp2261 const Register TReg = I.getOperand(2).getReg(); in select() local
2276 .addUse(TReg) in select()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp3023 const Register TReg = I.getOperand(2).getReg(); in select() local
3036 if (!emitSelect(I.getOperand(0).getReg(), TReg, FReg, AArch64CC::NE, MIB)) in select()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp32129 Register TReg = MRI->createVirtualRegister(&X86::GR64RegClass); in EmitSjLjDispatchBlock() local
32141 BuildMI(DispContBB, DL, TII->get(X86::ADD64rr), TReg) in EmitSjLjDispatchBlock()
32145 BuildMI(DispContBB, DL, TII->get(X86::JMP64r)).addReg(TReg); in EmitSjLjDispatchBlock()