| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RedundantCopyElimination.cpp | 105 unsigned TargetReg = CompBr->getOperand(0).getReg(); in optimizeCopy() local
106 if (!TargetReg) in optimizeCopy()
108 assert(TargetRegisterInfo::isPhysicalRegister(TargetReg) && in optimizeCopy()
113 for (MCRegAliasIterator AI(TargetReg, TRI, true); AI.isValid(); ++AI) in optimizeCopy()
118 unsigned SmallestDef = TargetReg; in optimizeCopy()
131 (TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) { in optimizeCopy()
145 if (MI->modifiesRegister(TargetReg, TRI)) in optimizeCopy()
158 MBB->addLiveIn(TargetReg); in optimizeCopy()
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in emitInstruction() local
187 emitMask(TargetReg, IndirectBranchMaskReg, STI); in emitInstruction()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 178 unsigned TargetReg = Inst.getOperand(1).getReg(); in EmitInstruction() local
179 emitMask(TargetReg, IndirectBranchMaskReg, STI); in EmitInstruction()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in EmitInstruction() local
187 emitMask(TargetReg, IndirectBranchMaskReg, STI); in EmitInstruction()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 993 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1024 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1044 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1111 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1116 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1124 TargetReg) in tracePredStateThroughIndirectBranches()
1136 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1144 unsigned TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1155 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1174 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 987 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1018 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1038 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1105 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1110 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1118 TargetReg) in tracePredStateThroughIndirectBranches()
1130 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1138 unsigned TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1149 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1168 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX8664.cpp | 721 RegNumT TargetReg = {}; in emitCallToTarget() local
728 TargetReg = Traits::RegisterSet::Reg_r11; in emitCallToTarget()
732 Variable *T = makeReg(IceType_i64, TargetReg); in emitCallToTarget()
736 Operand *T = legalizeToReg(CallTarget, TargetReg); in emitCallToTarget()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 301 Register TargetReg) { in buildGitPtr() argument
306 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
307 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
312 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
315 BuildMI(MBB, I, DL, GetPC64, TargetReg); in buildGitPtr()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 716 unsigned TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
724 .addReg(TargetReg) in expandEhReturn()
727 .addReg(TargetReg) in expandEhReturn()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 882 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
890 .addReg(TargetReg) in expandEhReturn()
893 .addReg(TargetReg) in expandEhReturn()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 896 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
904 .addReg(TargetReg) in expandEhReturn()
907 .addReg(TargetReg) in expandEhReturn()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 2101 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
2103 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
2104 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
2163 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2164 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
2185 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2186 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 2516 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
2518 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
2519 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
2603 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2604 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
2625 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2626 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 210 const SmallSet<unsigned, 2> &TargetReg,
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 214 const SmallSet<Register, 2> &TargetReg,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 2436 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
2438 MIB.buildInstr(AArch64::JumpTableDest32, {TargetReg, ScratchReg}, in selectBrJT()
2443 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 3198 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
3203 {TargetReg, ScratchReg}, {JTAddr, Index}) in selectBrJT()
3206 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 2553 Register TargetReg, Register InsertReg, in buildBitFieldInsert() argument
2555 LLT TargetTy = B.getMRI()->getType(TargetReg); in buildBitFieldInsert()
2569 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
|