| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 15 MCInst TmpInst;
17 TmpInst.setOpcode(Mips::AND_V);
20 TmpInst.addOperand(MCOp);
23 TmpInst.addOperand(MCOp);
26 TmpInst.addOperand(MCOp);
27 EmitToStreamer(OutStreamer, TmpInst);
31 MCInst TmpInst;
33 TmpInst.setOpcode(Mips::AND_V);
36 TmpInst.addOperand(MCOp);
39 TmpInst.addOperand(MCOp);
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 15 MCInst TmpInst;
17 TmpInst.setOpcode(ARM::Bcc);
20 TmpInst.addOperand(MCOp);
22 TmpInst.addOperand(MCOperand::createImm(14));
23 TmpInst.addOperand(MCOperand::createReg(0));
24 EmitToStreamer(OutStreamer, TmpInst);
28 MCInst TmpInst;
30 TmpInst.setOpcode(ARM::LDMIA_UPD);
33 TmpInst.addOperand(MCOp);
36 TmpInst.addOperand(MCOp);
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| /external/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 745 MCInst TmpInst; in ProcessInstruction() local
746 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
748 TmpInst.addOperand(MCOperand::createImm( in ProcessInstruction()
750 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
751 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction()
752 Inst = TmpInst; in ProcessInstruction()
757 MCInst TmpInst; in ProcessInstruction() local
758 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
759 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction()
760 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 720 MCInst TmpInst; in ProcessInstruction() local
721 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
723 TmpInst.addOperand(MCOperand::createImm( in ProcessInstruction()
725 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
726 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction()
727 Inst = TmpInst; in ProcessInstruction()
732 MCInst TmpInst; in ProcessInstruction() local
733 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
734 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction()
735 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 847 MCInst TmpInst; in ProcessInstruction() local
848 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
850 TmpInst.addOperand(MCOperand::createImm( in ProcessInstruction()
852 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
853 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction()
854 Inst = TmpInst; in ProcessInstruction()
859 MCInst TmpInst; in ProcessInstruction() local
860 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
861 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction()
862 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 287 MCInst TmpInst; in HexagonProcessInstruction() local
289 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
290 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
291 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
293 MappedInst = TmpInst; in HexagonProcessInstruction()
306 MCInst TmpInst; in HexagonProcessInstruction() local
308 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
309 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
310 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in HexagonProcessInstruction()
312 MappedInst = TmpInst; in HexagonProcessInstruction()
[all …]
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6832 MCInst TmpInst; in processInstruction() local
6833 TmpInst.setOpcode(Opcode); in processInstruction()
6834 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
6835 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6836 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
6837 TmpInst.addOperand(MCOperand::createReg(0)); in processInstruction()
6838 TmpInst.addOperand(MCOperand::createImm(0)); in processInstruction()
6839 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
6840 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
6841 Inst = TmpInst; in processInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 334 MCInst TmpInst; in HexagonProcessInstruction() local
336 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
337 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
338 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
340 MappedInst = TmpInst; in HexagonProcessInstruction()
350 MCInst TmpInst; in HexagonProcessInstruction() local
352 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
353 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
354 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in HexagonProcessInstruction()
356 MappedInst = TmpInst; in HexagonProcessInstruction()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 334 MCInst TmpInst; in HexagonProcessInstruction() local
336 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
337 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
338 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
340 MappedInst = TmpInst; in HexagonProcessInstruction()
350 MCInst TmpInst; in HexagonProcessInstruction() local
352 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
353 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
354 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in HexagonProcessInstruction()
356 MappedInst = TmpInst; in HexagonProcessInstruction()
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| /external/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 8543 MCInst TmpInst; in processInstruction() local
8544 TmpInst.setOpcode(Opcode); in processInstruction()
8545 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8546 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8547 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8548 TmpInst.addOperand(MCOperand::createReg(0)); in processInstruction()
8549 TmpInst.addOperand(MCOperand::createImm(0)); in processInstruction()
8550 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8551 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8552 Inst = TmpInst; in processInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 8256 MCInst TmpInst; in processInstruction() local
8257 TmpInst.setOpcode(Opcode); in processInstruction()
8258 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8259 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8263 TmpInst.addOperand(MCOperand::createImm(imm)); in processInstruction()
8265 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8266 TmpInst.addOperand(Inst.getOperand(4)); in processInstruction()
8267 Inst = TmpInst; in processInstruction()
8276 MCInst TmpInst; in processInstruction() local
8277 TmpInst.setOpcode(Opcode); in processInstruction()
[all …]
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 171 MCInst TmpInst; in emitR() local
172 TmpInst.setOpcode(Opcode); in emitR()
173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
174 TmpInst.setLoc(IDLoc); in emitR()
175 getStreamer().emitInstruction(TmpInst, *STI); in emitR()
180 MCInst TmpInst; in emitRX() local
181 TmpInst.setOpcode(Opcode); in emitRX()
182 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
183 TmpInst.addOperand(Op1); in emitRX()
184 TmpInst.setLoc(IDLoc); in emitRX()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 168 MCInst TmpInst; in emitR() local
169 TmpInst.setOpcode(Opcode); in emitR()
170 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
171 TmpInst.setLoc(IDLoc); in emitR()
172 getStreamer().EmitInstruction(TmpInst, *STI); in emitR()
177 MCInst TmpInst; in emitRX() local
178 TmpInst.setOpcode(Opcode); in emitRX()
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
180 TmpInst.addOperand(Op1); in emitRX()
181 TmpInst.setLoc(IDLoc); in emitRX()
[all …]
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1462 MCInst TmpInst; in makeCombineInst() local
1463 TmpInst.setOpcode(opCode); in makeCombineInst()
1464 TmpInst.addOperand(Rdd); in makeCombineInst()
1465 TmpInst.addOperand(MO1); in makeCombineInst()
1466 TmpInst.addOperand(MO2); in makeCombineInst()
1468 return TmpInst; in makeCombineInst()
1582 MCInst TmpInst; in processInstruction() local
1585 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1586 TmpInst.addOperand(Pd); in processInstruction()
1587 TmpInst.addOperand(Rt); in processInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1225 MCInst TmpInst; in makeCombineInst() local
1226 TmpInst.setOpcode(opCode); in makeCombineInst()
1227 TmpInst.addOperand(Rdd); in makeCombineInst()
1228 TmpInst.addOperand(MO1); in makeCombineInst()
1229 TmpInst.addOperand(MO2); in makeCombineInst()
1231 return TmpInst; in makeCombineInst()
1359 MCInst TmpInst; in processInstruction() local
1362 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1363 TmpInst.addOperand(Pd); in processInstruction()
1364 TmpInst.addOperand(Rt); in processInstruction()
[all …]
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| /external/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1236 MCInst TmpInst; in makeCombineInst() local
1237 TmpInst.setOpcode(opCode); in makeCombineInst()
1238 TmpInst.addOperand(Rdd); in makeCombineInst()
1239 TmpInst.addOperand(MO1); in makeCombineInst()
1240 TmpInst.addOperand(MO2); in makeCombineInst()
1242 return TmpInst; in makeCombineInst()
1389 MCInst TmpInst; in processInstruction() local
1392 TmpInst.setOpcode(Hexagon::C2_cmpeq); in processInstruction()
1393 TmpInst.addOperand(Pd); in processInstruction()
1394 TmpInst.addOperand(Rt); in processInstruction()
[all …]
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 131 MCInst TmpInst; in emitR() local
132 TmpInst.setOpcode(Opcode); in emitR()
133 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
134 TmpInst.setLoc(IDLoc); in emitR()
135 getStreamer().EmitInstruction(TmpInst, *STI); in emitR()
140 MCInst TmpInst; in emitRX() local
141 TmpInst.setOpcode(Opcode); in emitRX()
142 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
143 TmpInst.addOperand(Op1); in emitRX()
144 TmpInst.setLoc(IDLoc); in emitRX()
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| /external/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| D | RISCVMCCodeEmitter.cpp | 116 MCInst TmpInst; in expandFunctionCall() local
139 TmpInst = MCInstBuilder(RISCV::AUIPC) in expandFunctionCall()
142 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandFunctionCall()
148 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
151 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
152 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandFunctionCall()
186 MCInst TmpInst = MCInstBuilder(RISCV::ADD) in expandAddTPRel() local
190 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in expandAddTPRel()
197 MCInst TmpInst; in expandVMSGE() local
219 TmpInst = MCInstBuilder(Opcode) in expandVMSGE()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 538 MCInst TmpInst; in EmitInstruction() local
628 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, IsDarwin); in EmitInstruction()
630 unsigned PICR = TmpInst.getOperand(0).getReg(); in EmitInstruction()
653 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
660 const MCOperand TR = TmpInst.getOperand(1); in EmitInstruction()
661 const MCOperand PICR = TmpInst.getOperand(0); in EmitInstruction()
664 TmpInst.getOperand(1) = in EmitInstruction()
666 TmpInst.getOperand(0) = TR; in EmitInstruction()
667 TmpInst.getOperand(2) = PICR; in EmitInstruction()
668 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 479 MCInst TmpInst; in EmitInstruction() local
539 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); in EmitInstruction()
542 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
549 const MCOperand TR = TmpInst.getOperand(1); in EmitInstruction()
550 const MCOperand PICR = TmpInst.getOperand(0); in EmitInstruction()
553 TmpInst.getOperand(1) = in EmitInstruction()
555 TmpInst.getOperand(0) = TR; in EmitInstruction()
556 TmpInst.getOperand(2) = PICR; in EmitInstruction()
557 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
559 TmpInst.setOpcode(PPC::ADD4); in EmitInstruction()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 554 MCInst TmpInst; in emitInstruction() local
672 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); in emitInstruction()
674 unsigned PICR = TmpInst.getOperand(0).getReg(); in emitInstruction()
697 TmpInst.setOpcode(PPC::LWZ); in emitInstruction()
704 const MCOperand TR = TmpInst.getOperand(1); in emitInstruction()
705 const MCOperand PICR = TmpInst.getOperand(0); in emitInstruction()
708 TmpInst.getOperand(1) = in emitInstruction()
710 TmpInst.getOperand(0) = TR; in emitInstruction()
711 TmpInst.getOperand(2) = PICR; in emitInstruction()
712 EmitToStreamer(*OutStreamer, TmpInst); in emitInstruction()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAsmPrinter.cpp | 177 MCInst TmpInst; in emitCallInstruction() local
178 MCInstLowering.Lower(MI, TmpInst); in emitCallInstruction()
179 TmpInst.setOpcode(Lanai::BT); in emitCallInstruction()
180 OutStreamer->EmitInstruction(TmpInst, STI); in emitCallInstruction()
194 MCInst TmpInst; in customEmitInstruction() local
195 MCInstLowering.Lower(MI, TmpInst); in customEmitInstruction()
196 OutStreamer->EmitInstruction(TmpInst, STI); in customEmitInstruction()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAsmPrinter.cpp | 175 MCInst TmpInst; in emitCallInstruction() local
176 MCInstLowering.Lower(MI, TmpInst); in emitCallInstruction()
177 TmpInst.setOpcode(Lanai::BT); in emitCallInstruction()
178 OutStreamer->EmitInstruction(TmpInst, STI); in emitCallInstruction()
192 MCInst TmpInst; in customEmitInstruction() local
193 MCInstLowering.Lower(MI, TmpInst); in customEmitInstruction()
194 OutStreamer->EmitInstruction(TmpInst, STI); in customEmitInstruction()
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiAsmPrinter.cpp | 175 MCInst TmpInst; in emitCallInstruction() local
176 MCInstLowering.Lower(MI, TmpInst); in emitCallInstruction()
177 TmpInst.setOpcode(Lanai::BT); in emitCallInstruction()
178 OutStreamer->emitInstruction(TmpInst, STI); in emitCallInstruction()
192 MCInst TmpInst; in customEmitInstruction() local
193 MCInstLowering.Lower(MI, TmpInst); in customEmitInstruction()
194 OutStreamer->emitInstruction(TmpInst, STI); in customEmitInstruction()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1400 MCInst TmpInst; in EmitInstruction() local
1401 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in EmitInstruction()
1402 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
1419 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr)); in EmitInstruction()
1422 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL)); in EmitInstruction()
1423 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1425 TmpInst.addOperand(MCOperand::createReg(0)); in EmitInstruction()
1426 EmitToStreamer(*OutStreamer, TmpInst); in EmitInstruction()
1431 MCInst TmpInst; in EmitInstruction() local
1432 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel in EmitInstruction()
[all …]
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