/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64SpeculationHardening.cpp | 161 unsigned TmpReg) const; 307 unsigned TmpReg = RS.FindUnusedReg(&AArch64::GPR64commonRegClass); in instrumentControlFlow() local 309 << ((TmpReg == 0) ? "no register " : "register "); in instrumentControlFlow() 310 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " "; in instrumentControlFlow() 312 if (TmpReg == 0) in instrumentControlFlow() 315 ReturnInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow() 317 CallInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow() 384 unsigned TmpReg) const { in insertRegToSPTaintPropagation() 393 .addDef(TmpReg) in insertRegToSPTaintPropagation() 399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64SpeculationHardening.cpp | 161 unsigned TmpReg) const; 307 unsigned TmpReg = RS.FindUnusedReg(&AArch64::GPR64commonRegClass); in instrumentControlFlow() local 309 << ((TmpReg == 0) ? "no register " : "register "); in instrumentControlFlow() 310 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " "; in instrumentControlFlow() 312 if (TmpReg == 0) in instrumentControlFlow() 315 ReturnInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow() 317 CallInstructions.push_back({&MI, TmpReg}); in instrumentControlFlow() 384 unsigned TmpReg) const { in insertRegToSPTaintPropagation() 393 .addDef(TmpReg) in insertRegToSPTaintPropagation() 399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation() [all …]
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/external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
D | MipsAsmParser.cpp | 2728 unsigned TmpReg = DstReg; in loadImmediate() local 2736 TmpReg = ATReg; in loadImmediate() 2756 unsigned TmpReg = DstReg; in loadImmediate() local 2758 TmpReg = getATReg(IDLoc); in loadImmediate() 2759 if (!TmpReg) in loadImmediate() 2763 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate() 2765 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate() 2778 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate() 2779 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate() 2781 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
D | MipsAsmParser.cpp | 2700 unsigned TmpReg = DstReg; in loadImmediate() local 2708 TmpReg = ATReg; in loadImmediate() 2728 unsigned TmpReg = DstReg; in loadImmediate() local 2730 TmpReg = getATReg(IDLoc); in loadImmediate() 2731 if (!TmpReg) in loadImmediate() 2735 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate() 2737 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate() 2750 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate() 2751 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate() 2753 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate() [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 959 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local 960 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg() 962 SrcReg = TmpReg; in PPCMoveToFPReg() 1038 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local 1039 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP() 1042 SrcReg = TmpReg; in SelectIToFP() 1137 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); in SelectFPToI() local 1139 TII.get(TargetOpcode::COPY), TmpReg) in SelectFPToI() 1141 SrcReg = TmpReg; in SelectFPToI() 1348 unsigned TmpReg = createResultReg(RC); in processCallArgs() local [all …]
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/external/llvm/lib/Target/Mips/AsmParser/ |
D | MipsAsmParser.cpp | 2176 unsigned TmpReg = DstReg; in loadImmediate() local 2184 TmpReg = ATReg; in loadImmediate() 2204 unsigned TmpReg = DstReg; in loadImmediate() local 2206 TmpReg = getATReg(IDLoc); in loadImmediate() 2207 if (!TmpReg) in loadImmediate() 2211 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate() 2213 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate() 2227 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate() 2228 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate() 2230 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate() [all …]
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/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 158 unsigned TmpReg = createResultReg(ToRC); in copyRegToRegClass() local 160 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg); in copyRegToRegClass() 161 return TmpReg; in copyRegToRegClass() 1026 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local 1027 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg() 1029 SrcReg = TmpReg; in PPCMoveToFPReg() 1121 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local 1122 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP() 1125 SrcReg = TmpReg; in SelectIToFP() 1448 unsigned TmpReg = createResultReg(RC); in processCallArgs() local [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 157 unsigned TmpReg = createResultReg(ToRC); in copyRegToRegClass() local 159 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg); in copyRegToRegClass() 160 return TmpReg; in copyRegToRegClass() 1024 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local 1025 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg() 1027 SrcReg = TmpReg; in PPCMoveToFPReg() 1119 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local 1120 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP() 1123 SrcReg = TmpReg; in SelectIToFP() 1445 unsigned TmpReg = createResultReg(RC); in processCallArgs() local [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
D | AVRExpandPseudoInsts.cpp | 584 unsigned TmpReg = 0; // 0 for no temporary register in expand() local 593 TmpReg = scavengeGPR8(MI); in expand() 595 unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expand() 596 unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg; in expand() 604 if (TmpReg) in expand() 605 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand() 613 if (TmpReg) { in expand() 615 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg); in expand() 695 unsigned TmpReg = 0; // 0 for no temporary register in expand() local 709 TmpReg = scavengeGPR8(MI); in expand() [all …]
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/external/llvm-project/llvm/lib/Target/AVR/ |
D | AVRExpandPseudoInsts.cpp | 622 Register TmpReg = 0; // 0 for no temporary register in expand() local 631 TmpReg = scavengeGPR8(MI); in expand() 633 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expand() 634 Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg; in expand() 642 if (TmpReg) in expand() 643 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand() 651 if (TmpReg) { in expand() 653 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg); in expand() 733 Register TmpReg = 0; // 0 for no temporary register in expand() local 747 TmpReg = scavengeGPR8(MI); in expand() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIFixSGPRCopies.cpp | 299 Register TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local 302 TmpReg) in foldVGPRCopyIntoRegSequence() 312 .addReg(TmpReg, RegState::Kill); in foldVGPRCopyIntoRegSequence() 313 TmpReg = TmpAReg; in foldVGPRCopyIntoRegSequence() 316 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence() 623 Register TmpReg in runOnMachineFunction() local 627 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg) in runOnMachineFunction() 629 MI.getOperand(1).setReg(TmpReg); in runOnMachineFunction()
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/external/llvm/lib/Target/AMDGPU/ |
D | SIRegisterInfo.cpp | 518 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local 545 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex() 567 .addReg(TmpReg, RegState::Kill) // src in eliminateFrameIndex() 587 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local 615 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg) in eliminateFrameIndex() 623 .addReg(TmpReg, RegState::Kill) in eliminateFrameIndex() 668 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local 670 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex() 672 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
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D | SIFixSGPRCopies.cpp | 227 unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local 229 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), TmpReg) in foldVGPRCopyIntoRegSequence() 232 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
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/external/llvm/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 290 unsigned TmpReg = MRI->createVirtualRegister( in ExpandFPMLxInstruction() local 293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() 305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
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D | ThumbRegisterInfo.cpp | 570 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local 574 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex() 577 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex() 581 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex() 586 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 287 Register TmpReg = in ExpandFPMLxInstruction() local 290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() 302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
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D | ThumbRegisterInfo.cpp | 513 Register TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local 517 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex() 520 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex() 524 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex() 529 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 287 Register TmpReg = in ExpandFPMLxInstruction() local 290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() 302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
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D | ThumbRegisterInfo.cpp | 512 Register TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local 516 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex() 519 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex() 523 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex() 528 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | SIFixSGPRCopies.cpp | 297 Register TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local 300 TmpReg) in foldVGPRCopyIntoRegSequence() 310 .addReg(TmpReg, RegState::Kill); in foldVGPRCopyIntoRegSequence() 311 TmpReg = TmpAReg; in foldVGPRCopyIntoRegSequence() 314 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence() 620 Register TmpReg in runOnMachineFunction() local 624 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg) in runOnMachineFunction() 626 MI.getOperand(1).setReg(TmpReg); in runOnMachineFunction()
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D | SIRegisterInfo.cpp | 841 Register TmpReg; in buildSpillLoadStore() local 869 if (!TmpReg) { in buildSpillLoadStore() 872 TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in buildSpillLoadStore() 873 RS->setRegUsed(TmpReg); in buildSpillLoadStore() 877 TII->get(AMDGPU::V_ACCVGPR_READ_B32), TmpReg) in buildSpillLoadStore() 883 SubReg = TmpReg; in buildSpillLoadStore() 915 if (!IsStore && TmpReg != AMDGPU::NoRegister) { in buildSpillLoadStore() 918 .addReg(TmpReg, RegState::Kill); in buildSpillLoadStore() 1469 Register TmpReg = RS->scavengeRegister(RC, MI, 0, !UseSGPR); in eliminateFrameIndex() local 1470 FIOp.setReg(TmpReg); in eliminateFrameIndex() [all …]
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsTargetStreamer.cpp | 286 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset() argument 309 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset() 311 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset() 313 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset() 325 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithSymOffset() argument 333 emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); in emitLoadWithSymOffset() 335 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithSymOffset() 337 emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI); in emitLoadWithSymOffset()
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86SpeculativeLoadHardening.cpp | 1535 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() local 1539 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg) in mergePredStateIntoSP() 1546 .addReg(TmpReg, RegState::Kill); in mergePredStateIntoSP() 1556 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() local 1561 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg) in extractPredStateFromSP() 1565 .addReg(TmpReg, RegState::Kill) in extractPredStateFromSP() 1663 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() local 1698 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg) in hardenLoadAddr() 1729 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg) in hardenLoadAddr() 1742 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg) in hardenLoadAddr() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86SpeculativeLoadHardening.cpp | 1908 Register TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() local 1912 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg) in mergePredStateIntoSP() 1919 .addReg(TmpReg, RegState::Kill); in mergePredStateIntoSP() 1929 Register TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() local 1934 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg) in extractPredStateFromSP() 1938 .addReg(TmpReg, RegState::Kill) in extractPredStateFromSP() 2036 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() local 2071 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg) in hardenLoadAddr() 2102 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg) in hardenLoadAddr() 2115 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg) in hardenLoadAddr() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
D | LegalizationArtifactCombiner.h | 649 Register TmpReg; in lookThroughCopyInstrs() local 650 while (mi_match(Reg, MRI, m_Copy(m_Reg(TmpReg)))) { in lookThroughCopyInstrs() 651 if (MRI.getType(TmpReg).isValid()) in lookThroughCopyInstrs() 652 Reg = TmpReg; in lookThroughCopyInstrs()
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