Searched refs:TruePred (Results 1 – 13 of 13) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 53 MCReturnStatement<TruePred>>,
56 MCReturnStatement<TruePred>>],
69 MCReturnStatement<TruePred>>,
72 MCReturnStatement<TruePred>>],
90 MCReturnStatement<TruePred>>,
93 MCReturnStatement<TruePred>>],
128 MCReturnStatement<TruePred>>,
154 MCReturnStatement<TruePred>>],
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 53 MCReturnStatement<TruePred>>,
56 MCReturnStatement<TruePred>>],
69 MCReturnStatement<TruePred>>,
72 MCReturnStatement<TruePred>>],
90 MCReturnStatement<TruePred>>,
93 MCReturnStatement<TruePred>>],
128 MCReturnStatement<TruePred>>,
154 MCReturnStatement<TruePred>>],
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| /external/llvm-project/llvm/lib/Transforms/InstCombine/ |
| D | InstCombinePHI.cpp | 1249 BasicBlock *TruePred = nullptr, *FalsePred = nullptr; in SimplifyUsingControlFlow() local
1253 TruePred = Pred; in SimplifyUsingControlFlow()
1257 assert(TruePred && FalsePred && "Must be!"); in SimplifyUsingControlFlow()
1271 BasicBlockEdge TrueIncEdge(TruePred, BB); in SimplifyUsingControlFlow()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ScheduleBdVer2.td | 1341 SchedVar<MCSchedPredicate<TruePred>, [WriteALU]>
1348 SchedVar<MCSchedPredicate<TruePred>, [WriteFLogic]>
1359 SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogic]>
1365 SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogicX]>
1372 SchedVar<MCSchedPredicate<TruePred>, [WriteVecALU]>
1382 SchedVar<MCSchedPredicate<TruePred>, [WriteVecALUX]>
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| D | X86ScheduleBtVer2.td | 1046 ], TruePred >
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleBdVer2.td | 1306 SchedVar<MCSchedPredicate<TruePred>, [WriteALU]>
1313 SchedVar<MCSchedPredicate<TruePred>, [WriteFLogic]>
1324 SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogic]>
1330 SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogicX]>
1337 SchedVar<MCSchedPredicate<TruePred>, [WriteVecALU]>
1347 SchedVar<MCSchedPredicate<TruePred>, [WriteVecALUX]>
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| D | X86ScheduleBtVer2.td | 1043 ], TruePred >
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetInstrPredicate.td | 78 def TruePred : MCTrue;
149 // Otherwise, it simply evaluates to TruePred.
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| D | TargetSchedule.td | 379 def NoSchedPred : MCSchedPredicate<TruePred>;
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| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetInstrPredicate.td | 78 def TruePred : MCTrue;
154 // Otherwise, it simply evaluates to TruePred.
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| D | TargetSchedule.td | 379 def NoSchedPred : MCSchedPredicate<TruePred>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 3050 BasicBlock *TruePred = QTB ? QTB : QFB->getSinglePredecessor(); in mergeConditionalStoreToAddress() local
3051 BasicBlock *NewBB = SplitBlockPredecessors(PostBB, { QFB, TruePred}, in mergeConditionalStoreToAddress()
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| /external/llvm-project/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 3218 BasicBlock *TruePred = QTB ? QTB : QFB->getSinglePredecessor(); in mergeConditionalStoreToAddress() local
3219 BasicBlock *NewBB = SplitBlockPredecessors(PostBB, { QFB, TruePred}, in mergeConditionalStoreToAddress()
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