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Searched refs:TrueReg (Results 1 – 25 of 41) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp757 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
770 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
795 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in insertSelect() argument
803 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
855 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
856 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
2224 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
2231 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
2233 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
2235 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
DPPCMIPeephole.cpp459 unsigned TrueReg = in simplifyCode() local
461 if (!Register::isVirtualRegister(TrueReg)) in simplifyCode()
463 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
522 unsigned TrueReg = in simplifyCode() local
524 if (!Register::isVirtualRegister(TrueReg)) in simplifyCode()
526 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
DPPCInstrInfo.h279 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp620 unsigned TrueReg = in simplifyCode() local
622 if (!Register::isVirtualRegister(TrueReg)) in simplifyCode()
624 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
683 unsigned TrueReg = in simplifyCode() local
685 if (!Register::isVirtualRegister(TrueReg)) in simplifyCode()
687 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
DPPCInstrInfo.cpp1098 Register DstReg, Register TrueReg, in canInsertSelect() argument
1112 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1137 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
1145 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1197 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1198 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
2664 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
2671 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
2673 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
2675 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp787 auto TrueReg = MIB.getReg(2); in selectSelect() local
789 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
794 .addUse(TrueReg) in selectSelect()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h181 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
DPPCInstrInfo.cpp687 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
703 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
728 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in insertSelect() argument
739 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
792 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h158 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
DAArch64InstrInfo.cpp368 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, in canInsertSelect() argument
373 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
387 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
411 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
514 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
519 TrueReg = FalseReg; in insertSelect()
533 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
537 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( in insertSelect()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp724 unsigned TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
725 if (TrueReg == 0) in selectSelect()
733 std::swap(TrueReg, FalseReg); in selectSelect()
763 .addReg(TrueReg) in selectSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp789 auto TrueReg = MIB->getOperand(2).getReg(); in selectSelect() local
791 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
796 .addUse(TrueReg) in selectSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp535 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
570 unsigned TrueReg, in insertSelect() argument
590 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
592 TrueReg = TReg; in insertSelect()
604 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
DSystemZInstrInfo.h228 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.h243 ArrayRef<MachineOperand> Cond, Register TrueReg,
DSystemZInstrInfo.cpp535 Register DstReg, Register TrueReg, in canInsertSelect() argument
548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
571 Register TrueReg, in insertSelect() argument
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
593 TrueReg = TReg; in insertSelect()
605 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h690 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
714 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp902 unsigned TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
903 if (TrueReg == 0) in selectSelect()
911 std::swap(TrueReg, FalseReg); in selectSelect()
953 .addReg(TrueReg) in selectSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp895 unsigned TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
896 if (TrueReg == 0) in selectSelect()
904 std::swap(TrueReg, FalseReg); in selectSelect()
938 .addReg(TrueReg) in selectSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h297 unsigned TrueReg, unsigned FalseReg,
304 unsigned TrueReg, unsigned FalseReg) const override;
309 unsigned TrueReg, unsigned FalseReg) const;
DSIInstrInfo.cpp823 unsigned TrueReg, in insertVectorSelect() argument
841 .addReg(TrueReg) in insertVectorSelect()
856 .addReg(TrueReg) in insertVectorSelect()
870 .addReg(TrueReg) in insertVectorSelect()
884 .addReg(TrueReg) in insertVectorSelect()
896 .addReg(TrueReg) in insertVectorSelect()
916 .addReg(TrueReg) in insertVectorSelect()
934 .addReg(TrueReg) in insertVectorSelect()
2128 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
2135 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h304 Register TrueReg, Register FalseReg, int &CondCycles,
310 Register TrueReg, Register FalseReg) const override;
315 Register TrueReg, Register FalseReg) const;
DSIInstrInfo.cpp1036 Register TrueReg, in insertVectorSelect() argument
1052 .addReg(TrueReg) in insertVectorSelect()
1067 .addReg(TrueReg) in insertVectorSelect()
1081 .addReg(TrueReg) in insertVectorSelect()
1095 .addReg(TrueReg) in insertVectorSelect()
1107 .addReg(TrueReg) in insertVectorSelect()
1127 .addReg(TrueReg) in insertVectorSelect()
1145 .addReg(TrueReg) in insertVectorSelect()
2459 Register DstReg, Register TrueReg, in canInsertSelect() argument
2466 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h197 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h847 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in canInsertSelect() argument
871 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument

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