| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-uaddsat.mir | 35 ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
36 ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
47 ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
48 ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
89 ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
90 ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
101 ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
102 ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
178 ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
179 ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C3]](s16)
[all …]
|
| D | irtranslator-sat.ll | 13 ; CHECK: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]
14 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)
30 ; CHECK: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]]
31 ; CHECK: $vgpr0 = COPY [[UADDSAT]](s32)
50 ; CHECK: [[UADDSAT:%[0-9]+]]:_(s64) = G_UADDSAT [[MV]], [[MV1]]
51 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](s64)
72 ; CHECK: [[UADDSAT:%[0-9]+]]:_(<2 x s32>) = G_UADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
73 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](<2 x s32>)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 1930 { ISD::UADDSAT, MVT::v32i16, 1 }, in getIntrinsicInstrCost()
1931 { ISD::UADDSAT, MVT::v64i8, 1 }, in getIntrinsicInstrCost()
1948 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd in getIntrinsicInstrCost()
1949 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq in getIntrinsicInstrCost()
1950 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq in getIntrinsicInstrCost()
1951 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq in getIntrinsicInstrCost()
1991 { ISD::UADDSAT, MVT::v16i16, 1 }, in getIntrinsicInstrCost()
1992 { ISD::UADDSAT, MVT::v32i8, 1 }, in getIntrinsicInstrCost()
1993 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd in getIntrinsicInstrCost()
2028 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getIntrinsicInstrCost()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 266 SADDSAT, UADDSAT, enumerator
|
| D | TargetLowering.h | 2258 case ISD::UADDSAT: in isCommutativeBinOp()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 321 UADDSAT, enumerator
|
| D | TargetLowering.h | 2425 case ISD::UADDSAT: in isCommutativeBinOp()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2335 { ISD::UADDSAT, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2336 { ISD::UADDSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2395 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd in getTypeBasedIntrinsicInstrCost()
2396 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq in getTypeBasedIntrinsicInstrCost()
2397 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq in getTypeBasedIntrinsicInstrCost()
2398 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq in getTypeBasedIntrinsicInstrCost()
2403 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2404 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2464 { ISD::UADDSAT, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2465 { ISD::UADDSAT, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 453 case ISD::UADDSAT: in LegalizeOp()
838 case ISD::UADDSAT: in Expand()
|
| D | SelectionDAGDumper.cpp | 312 case ISD::UADDSAT: return "uaddsat"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 159 case ISD::UADDSAT: in PromoteIntegerResult()
744 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSHLSAT()
764 case ISD::UADDSAT: in PromoteIntRes_ADDSUBSHLSAT()
793 if (Opcode == ISD::UADDSAT) { in PromoteIntRes_ADDSUBSHLSAT()
2139 case ISD::UADDSAT: in ExpandIntegerResult()
|
| D | LegalizeVectorTypes.cpp | 129 case ISD::UADDSAT: in ScalarizeVectorResult()
997 case ISD::UADDSAT: in SplitVectorResult()
2887 case ISD::UADDSAT: in WidenVectorResult()
|
| D | TargetLowering.cpp | 7553 if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { in expandAddSubSat()
7564 case ISD::UADDSAT: in expandAddSubSat()
7592 if (Opcode == ISD::UADDSAT) { in expandAddSubSat()
|
| D | LegalizeDAG.cpp | 1135 case ISD::UADDSAT: in LegalizeOp()
3544 case ISD::UADDSAT: in ExpandNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 306 case ISD::UADDSAT: return "uaddsat"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 456 case ISD::UADDSAT: in LegalizeOp()
948 case ISD::UADDSAT: in Expand()
|
| D | LegalizeIntegerTypes.cpp | 154 case ISD::UADDSAT: in PromoteIntegerResult()
681 if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSAT()
698 case ISD::UADDSAT: in PromoteIntRes_ADDSUBSAT()
725 if (Opcode == ISD::UADDSAT) { in PromoteIntRes_ADDSUBSAT()
1907 case ISD::UADDSAT: in ExpandIntegerResult()
|
| D | LegalizeVectorTypes.cpp | 126 case ISD::UADDSAT: in ScalarizeVectorResult()
936 case ISD::UADDSAT: in SplitVectorResult()
2727 case ISD::UADDSAT: in WidenVectorResult()
|
| D | TargetLowering.cpp | 7108 if (Opcode == ISD::UADDSAT && isOperationLegalOrCustom(ISD::UMIN, VT)) { in expandAddSubSat()
7119 case ISD::UADDSAT: in expandAddSubSat()
7142 if (Opcode == ISD::UADDSAT) { in expandAddSubSat()
|
| D | LegalizeDAG.cpp | 1123 case ISD::UADDSAT: in LegalizeOp()
3411 case ISD::UADDSAT: in ExpandNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 654 setOperationAction(ISD::UADDSAT, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 128 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 764 setOperationAction(ISD::UADDSAT, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 133 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 493 setOperationAction(ISD::UADDSAT, MVT::i32, Legal); in SITargetLowering()
556 setOperationAction(ISD::UADDSAT, MVT::i16, Legal); in SITargetLowering()
722 setOperationAction(ISD::UADDSAT, MVT::v2i16, Legal); in SITargetLowering()
754 setOperationAction(ISD::UADDSAT, MVT::v4i16, Custom); in SITargetLowering()
4585 case ISD::UADDSAT: in LowerOperation()
|