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Searched refs:UD (Results 1 – 25 of 254) sorted by relevance

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/external/mesa3d/src/intel/tools/tests/gen7/
Dand.asm1 and(1) g11<1>UD g0.2<0,1,0>UD 0x007f0000UD { align1 1N };
2 and(1) g12.2<1>UD g0.2<0,1,0>UD 0x0000f000UD { align1 WE_all 1N };
3 and(8) g13<1>UD g6<0>UD g5.4<0>.zUD { align16 1Q };
5 and(8) g22<1>UD g21<8,8,1>UD g20<8,8,1>UD { align1 1Q };
6 and.nz.f0.0(8) null<1>UD g24<8,8,1>UD g25<8,8,1>UD { align1 1Q };
7 and(16) g41<1>UD g39<8,8,1>UD g37<8,8,1>UD { align1 1H };
8 and.nz.f0.0(16) null<1>UD g45<8,8,1>UD g47<8,8,1>UD { align1 1H };
9 and(8) g12<1>UD g11<8,8,1>UD 0x00000001UD { align1 1Q };
10 and(16) g19<1>UD g17<8,8,1>UD 0x00000001UD { align1 1H };
11 and(8) g8<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1Q };
[all …]
Dor.asm1 or(1) g113.5<1>UD g0.5<0,1,0>UD 0x0000ff00UD { align1 WE_all 1N };
4 or(8) g10<1>UD g9<8,8,1>UD g8<8,8,1>UD { align1 1Q };
5 or(16) g16<1>UD g14<8,8,1>UD g12<8,8,1>UD { align1 1H };
7 or.nz.f0.0(8) g8<1>UD g4<8,8,1>UD g7<8,8,1>UD { align1 1Q };
8 or.nz.f0.0(8) null<1>UD g12<8,8,1>UD g15<8,8,1>UD { align1 1Q };
9 or.nz.f0.0(16) g12<1>UD g5<8,8,1>UD g10<8,8,1>UD { align1 1H };
10 or.nz.f0.0(16) null<1>UD g20<8,8,1>UD g26<8,8,1>UD { align1 1H };
11 (+f0.0) or(8) g6<1>UD g6<8,8,1>UD 0x3f800000UD { align1 1Q };
12 (+f0.0) or(16) g8<1>UD g8<8,8,1>UD 0x3f800000UD { align1 1H };
13 or(1) a0<1>UD g8<0,1,0>UD 0x02427000UD { align1 WE_all 1N };
[all …]
Dsend.asm5 send(8) g2<1>UW g8<8,8,1>UD 0x08427001
7 send(16) g2<1>UW g14<8,8,1>UD 0x10847001
9 send(8) g50<1>D g51<4>UD 0x02194013
11 send(8) null<1>F g12<4>UD 0x04094019
13 send(8) null<1>F g13<4>UD 0x04094011
15 send(8) null<1>F g12<4>UD 0x04094009
17 send(8) null<1>F g12<4>UD 0x04094001
19 send(8) g14<1>D g15<4>UD 0x0219400b
21 send(8) g13<1>D g12<4>UD 0x02194003
23 send(8) null<1>UW g12<4,4,1>UD 0x02008004
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dand.asm1 and(8) g4<1>UD g2<0,1,0>UD g3<8,8,1>UD { align1 1Q };
2 and(16) g5<1>UD g2<0,1,0>UD g3<8,8,1>UD { align1 1H };
3 and(1) g11<1>UD g0.2<0,1,0>UD 0x00fe0000UD { align1 1N };
4 and(1) g12.2<1>UD g0.2<0,1,0>UD 0x0001e000UD { align1 WE_all 1N };
5 and(8) g8<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1Q };
6 and(16) g20<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1H };
7 and(8) g16<1>UD g14<8,8,1>UD 0xfffffff4UD { align1 1Q };
8 and(16) g22<1>UD g18<8,8,1>UD 0xfffffff4UD { align1 1H };
9 and(8) g11<1>UD g1<0>UD g10<4>UD { align16 1Q };
11 and.nz.f0.0(8) null<1>UD g24<8,8,1>UD g25<8,8,1>UD { align1 1Q };
[all …]
Dor.asm1 or(1) g113.5<1>UD g0.5<0,1,0>UD 0x0000ff00UD { align1 WE_all 1N };
4 or.nz.f0.0(8) null<1>UD g12<8,8,1>UD g6<8,8,1>UD { align1 1Q };
5 or.nz.f0.0(16) null<1>UD g4<8,8,1>UD g2<8,8,1>UD { align1 1H };
6 or(8) g20<1>UD g19<8,8,1>UD g17<8,8,1>UD { align1 1Q };
7 or(16) g30<1>UD g28<8,8,1>UD g24<8,8,1>UD { align1 1H };
8 or(1) g2<1>UD g2<0,1,0>UD g4<0,1,0>UD { align1 WE_all 1N };
9 or(1) a0<1>UD g2<0,1,0>UD 0x064a7000UD { align1 WE_all 1N };
10 (+f0.0) or(8) g3<1>UD g3<8,8,1>UD 0x3f800000UD { align1 1Q };
11 (+f0.0) or(16) g3<1>UD g3<8,8,1>UD 0x3f800000UD { align1 1H };
13 or(1) a0<1>UD a0<0,1,0>UD g15<0,1,0>UD { align1 WE_all 1N };
[all …]
Dsend.asm5 send(8) g124<1>UW g13<8,8,1>UD 0x08427001
7 send(16) g120<1>UW g10<8,8,1>UD 0x10847001
9 send(8) g50<1>D g51<4>UD 0x02194013
11 send(8) null<1>F g12<4>UD 0x04094019
13 send(8) null<1>F g13<4>UD 0x04094011
15 send(8) null<1>F g12<4>UD 0x04094009
17 send(8) null<1>F g12<4>UD 0x04094001
19 send(8) g14<1>D g15<4>UD 0x0219400b
21 send(8) g13<1>D g12<4>UD 0x02194003
23 send(8) null<1>UW g12<4,4,1>UD 0x02008004
[all …]
Dsel.asm1 (+f0.0) sel(8) g47<1>UD g12<4>UD g13<4>UD { align16 1Q };
3 (+f0.0.any4h) sel(8) g30<1>UD g13<4>UD g12<4>UD { align16 1Q };
4 (+f0.0.all4h) sel(8) g16<1>UD g8<4>UD g9<4>UD { align16 1Q };
5 (+f0.0) sel(8) g23<1>UD g8<8,8,1>UD g23<8,8,1>UD { align1 1Q };
6 (+f0.0) sel(16) g42<1>UD g76<8,8,1>UD g78<8,8,1>UD { align1 1H };
7 sel.l(8) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1Q };
8 sel.l(16) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1H };
13 (+f0.0) sel(8) g124<1>UD g67<8,8,1>UD 0x3f800000UD { align1 1Q };
14 (+f0.0) sel(16) g120<1>UD g27<8,8,1>UD 0x3f800000UD { align1 1H };
16 (-f0.0) sel(8) g16<1>UD g20<8,8,1>UD 0x00000000UD { align1 1Q };
[all …]
Dshr.asm1 shr(1) g11<1>UD g11<0,1,0>UD 0x00000010UD { align1 1N };
2 shr(8) g20<1>UD g19<8,8,1>UD 0x00000001UD { align1 1Q };
3 shr(16) g88<1>UD g86<8,8,1>UD 0x00000001UD { align1 1H };
5 shr(8) g3<1>UD g2<0,1,0>UD g2.2<0,1,0>UD { align1 1Q };
6 shr(16) g3<1>UD g2<0,1,0>UD g2.2<0,1,0>UD { align1 1H };
8 shr(1) g29<1>UD g29<0,1,0>UD 5D { align1 WE_all 1N };
10 shr(8) g19<2>UW g5<8,8,1>UD g4<8,8,1>UW { align1 1Q };
11 shr(8) g23<2>UW g16<8,8,1>UD g13.8<8,8,1>UW { align1 2Q };
/external/mesa3d/src/intel/tools/tests/gen9/
Dor.asm1 or(8) g53<1>UD g49<8,8,1>UD g21<8,8,1>UD { align1 1Q };
2 or.nz.f0.0(8) null<1>UD g21<8,8,1>UD g2<8,8,1>UD { align1 1Q };
3 or.nz.f0.0(8) g5<1>UD g62<8,8,1>UD g67<8,8,1>UD { align1 1Q };
4 or(8) g5<1>UD g106.1<8,4,2>UD 0x7ff00000UD { align1 2Q };
5 or.nz.f0.0(16) null<1>UD g35<8,8,1>UD g32<8,8,1>UD { align1 1H };
6 or(16) g36<1>UD g34<8,8,1>UD g20<8,8,1>UD { align1 1H };
7 or.nz.f0.0(16) g53<1>UD g51<8,8,1>UD g49<8,8,1>UD { align1 1H };
8 or(1) g8<1>UD g8<0,1,0>UD g4<0,1,0>UD { align1 WE_all 1N };
9 or(1) a0<1>UD g8<0,1,0>UD 0x060ba000UD { align1 WE_all 1N };
10 (+f0.0) or(8) g3<1>UD g3<8,8,1>UD 0x3f800000UD { align1 1Q };
[all …]
Dsend.asm7 send(16) g9<1>UD g2<0,1,0>UD 0x02280300
13 send(8) g124<1>UW g13<8,8,1>UD 0x0643a001
15 send(16) g120<1>UW g23<8,8,1>UD 0x0c85a001
17 send(8) g10<1>UD g2<8,8,1>UD 0x02480028
23 send(8) g2<1>UW g10<8,8,1>UD 0x08427001
25 send(16) g2<1>UW g18<8,8,1>UD 0x10847001
27 send(8) null<1>F g11<8,8,1>UD 0x0c0a0037
29 send(8) null<1>F g6<8,8,1>UD 0x0a080027
31 send(8) null<1>F g6<8,8,1>UD 0x0c088017
33 send(8) null<1>F g6<8,8,1>UD 0x0a088017
[all …]
Dand.asm1 and(8) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1Q };
2 and(16) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1H };
3 and(8) g8<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1Q };
4 and(16) g18<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1H };
5 and(1) g7<1>UD g5<0,1,0>UD 0x000000f0UD { align1 WE_all 1N };
6 and.nz.f0.0(8) null<1>UD g36<8,8,1>UD g37<8,8,1>UD { align1 1Q };
7 and.nz.f0.0(16) null<1>UD g70<8,8,1>UD g72<8,8,1>UD { align1 1H };
8 and.z.f0.0(16) g21<1>UD g19<8,8,1>UD g17<8,8,1>UD { align1 1H };
9 and(8) g61<1>UD g79<8,8,1>UD g32.1<8,4,2>UD { align1 2Q };
12 and(1) a0<1>UD g4<0,1,0>UD 0x000000ffUD { align1 WE_all 1N };
[all …]
Dcr0.asm1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
Dshl.asm3 shl(1) g8<1>UD g5<0,1,0>UD 0x00000008UD { align1 WE_all 1N };
4 shl(8) g4<1>UD g6<8,8,1>UD g3<8,8,1>UD { align1 1Q };
5 shl(1) a0<1>UD g43<0,1,0>UD 0x00000002UD { align1 WE_all 1N };
7 shl(8) g26<1>UD g34<8,8,1>UW 0x00000002UD { align1 1Q };
8 shl(8) g3<1>UD g23<8,8,1>UD g21<8,8,1>UD { align1 WE_all 1Q };
9 shl(16) g10<1>UD g10<8,8,1>UD 0x00000010UD { align1 1H };
10 shl(1) g14<1>UD g21<0,1,0>UD 0x00000008UD { align1 WE_all 3N };
11 shl(8) g11<1>Q g5<4,4,1>Q g3<4,4,1>UD { align1 1Q };
12 shl(1) a0<1>UD g13<0,1,0>D 0x00000002UD { align1 WE_all 1N };
13 shl(8) g22<1>Q g8<4,4,1>Q g4<4,4,1>UD { align1 2Q };
Dmov.asm1 mov(8) g123<1>UD g1<8,8,1>UD { align1 WE_all 1Q };
3 mov(8) g14<1>UD 0x00000000UD { align1 1Q };
7 mov(8) g21<1>D g59<8,4,2>UD { align1 1Q };
10 mov(1) g2.2<1>UD 0x00000000UD { align1 WE_all 1N };
19 mov(16) g20<1>UD g0.1<0,1,0>UD { align1 1H };
28 mov(8) g92<2>UD g6.4<0,1,0>UD { align1 1Q };
34 mov(8) g127<1>UD g106.1<8,4,2>UD { align1 2Q };
36 mov(8) g33<1>D g34<8,4,2>UD { align1 2Q };
37 mov(8) g6<2>UD 0x00000000UD { align1 2Q };
39 mov(8) g12<1>UD g2<8,8,1>UW { align1 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen8/
Dand.asm1 and(8) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1Q };
2 and(16) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1H };
3 and(8) g8<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1Q };
4 and(16) g20<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1H };
5 and.z.f0.0(8) g9<1>UD g8<8,8,1>UD 0x00000003UD { align1 1Q };
7 and.z.f0.0(8) null<1>UD g13<8,8,1>UD g12<8,8,1>UD { align1 1Q };
8 and.nz.f0.0(8) null<1>UD g4.1<0,1,0>UD g19<8,8,1>UD { align1 1Q };
9 and.z.f0.0(16) null<1>UD g27<8,8,1>UD g18<8,8,1>UD { align1 1H };
10 and.nz.f0.0(16) null<1>UD g6.1<0,1,0>UD g22<8,8,1>UD { align1 1H };
11 and(1) g7<1>UD g5<0,1,0>UD 0x000000f0UD { align1 WE_all 1N };
[all …]
Dor.asm1 or(8) g53<1>UD g49<8,8,1>UD g21<8,8,1>UD { align1 1Q };
2 or.nz.f0.0(8) null<1>UD g21<8,8,1>UD g2<8,8,1>UD { align1 1Q };
3 or.nz.f0.0(8) g5<1>UD g62<8,8,1>UD g67<8,8,1>UD { align1 1Q };
4 or(8) g5<1>UD g106.1<8,4,2>UD 0x7ff00000UD { align1 2Q };
5 or.nz.f0.0(16) null<1>UD g35<8,8,1>UD g32<8,8,1>UD { align1 1H };
6 or(16) g36<1>UD g34<8,8,1>UD g20<8,8,1>UD { align1 1H };
7 or.nz.f0.0(16) g56<1>UD g54<8,8,1>UD g52<8,8,1>UD { align1 1H };
8 or(1) g2<1>UD g2<0,1,0>UD g4<0,1,0>UD { align1 WE_all 1N };
9 or(1) a0<1>UD g2<0,1,0>UD 0x064a7000UD { align1 WE_all 1N };
10 (+f0.0) or(8) g3<1>UD g3<8,8,1>UD 0x3f800000UD { align1 1Q };
[all …]
Dcr0.asm1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
Dsend.asm7 send(16) g9<1>UD g2<8,8,1>UD 0x02280300
11 send(8) null<1>UW g3<8,8,1>UD 0x0e0b5001
13 send(8) null<1>UW g1<8,8,1>UD 0x0e0b6001
17 send(8) g124<1>UW g13<8,8,1>UD 0x08427001
19 send(16) g120<1>UW g10<8,8,1>UD 0x10847001
21 send(8) g10<1>UD g2<8,8,1>UD 0x02480028
27 send(8) null<1>F g11<8,8,1>UD 0x0c0a0037
29 send(8) null<1>F g6<8,8,1>UD 0x0a080027
31 send(8) null<1>F g6<8,8,1>UD 0x0c088017
33 send(8) null<1>F g6<8,8,1>UD 0x0a088017
[all …]
Dmov.asm1 mov(8) g123<1>UD g1<8,8,1>UD { align1 WE_all 1Q };
3 mov(8) g14<1>UD 0x00000000UD { align1 1Q };
7 mov(8) g21<1>D g59<8,4,2>UD { align1 1Q };
10 mov(1) g2.2<1>UD 0x00000000UD { align1 WE_all 1N };
18 mov(16) g27<1>UD g0.1<0,1,0>UD { align1 1H };
19 mov(8) g3<1>UD 0D { align1 WE_all 1Q };
20 mov(1) g3.7<1>UD -1D { align1 WE_all 1N };
22 mov(8) g1<1>UD 0D { align1 WE_all 2Q };
25 mov(1) g1.7<1>UD -1D { align1 WE_all 3N };
32 mov(8) g92<2>UD g6.4<0,1,0>UD { align1 1Q };
[all …]
Dshl.asm3 shl(1) g2<1>UD g5<0,1,0>UD 0x00000008UD { align1 WE_all 1N };
4 shl(8) g4<1>UD g6<8,8,1>UD g3<8,8,1>UD { align1 1Q };
5 shl(1) a0<1>UD g27<0,1,0>UD 0x00000002UD { align1 WE_all 1N };
7 shl(8) g26<1>UD g34<8,8,1>UW 0x00000002UD { align1 1Q };
8 shl(8) g3<1>UD g23<8,8,1>UD g21<8,8,1>UD { align1 WE_all 1Q };
9 shl(16) g10<1>UD g10<8,8,1>UD 0x00000010UD { align1 1H };
10 shl(1) g22<1>UD g22<0,1,0>UD 0x00000004UD { align1 WE_all 3N };
11 shl(8) g11<1>Q g5<4,4,1>Q g3<4,4,1>UD { align1 1Q };
12 shl(1) a0<1>UD g13<0,1,0>D 0x00000002UD { align1 WE_all 1N };
13 shl(8) g22<1>Q g8<4,4,1>Q g4<4,4,1>UD { align1 2Q };
/external/mesa3d/src/intel/tools/tests/gen6/
Dor.asm1 or(8) g29<1>UD g9<4>.xUD 0x00000014UD { align16 1Q };
2 or(8) g43<1>UD g44<4>UD 1D { align16 1Q };
3 or(1) g28<1>UD g28<0,1,0>UD g57<0,1,0>UD { align1 1N };
4 or(8) g10<1>UD g9<8,8,1>UD g8<8,8,1>UD { align1 1Q };
5 or(16) g16<1>UD g14<8,8,1>UD g12<8,8,1>UD { align1 1H };
6 or(1) g9<1>UD g0<0,1,0>UD 0x00000800UD { align1 WE_all 1N };
8 or.nz.f0.0(8) null<1>UD g16<8,8,1>UD g17<8,8,1>UD { align1 1Q };
9 (+f0.0) or(8) g18<1>UD g18<8,8,1>UD 0x3f800000UD { align1 1Q };
10 or.nz.f0.0(16) null<1>UD g28<8,8,1>UD g30<8,8,1>UD { align1 1H };
11 (+f0.0) or(16) g31<1>UD g31<8,8,1>UD 0x3f800000UD { align1 1H };
[all …]
Dand.asm1 and(8) g22<1>UD g21<8,8,1>UD g20<8,8,1>UD { align1 1Q };
2 and.nz.f0.0(8) null<1>UD g24<8,8,1>UD g25<8,8,1>UD { align1 1Q };
3 and(16) g41<1>UD g39<8,8,1>UD g37<8,8,1>UD { align1 1H };
4 and.nz.f0.0(16) null<1>UD g45<8,8,1>UD g47<8,8,1>UD { align1 1H };
5 and(1) g28<1>UD g55<0,1,0>UD 0x0000ffffUD { align1 1N };
7 and(8) g12<1>UD g11<8,8,1>UD 0x00000001UD { align1 1Q };
8 and(16) g19<1>UD g17<8,8,1>UD 0x00000001UD { align1 1H };
12 and(1) g22<1>UD g0<0,1,0>UD 0x000000c0UD { align1 WE_all 1N };
15 and.nz.f0.0(8) null<1>UD g4<0,1,0>UD 0x00000001UD { align1 1Q };
16 and.nz.f0.0(16) null<1>UD g6<0,1,0>UD 0x00000001UD { align1 1H };
[all …]
Dsel.asm1 (+f0.0) sel(8) g40<1>UD g5<4>UD g6<4>UD { align16 1Q };
2 (-f0.0) sel(8) g6<1>UD g13<8,8,1>UD 0x00000000UD { align1 1Q };
3 (-f0.0) sel(16) g7<1>UD g9<8,8,1>UD 0x00000000UD { align1 1H };
4 (+f0.0) sel(8) g2<1>UD g31<8,8,1>UD g34<8,8,1>UD { align1 1Q };
5 (+f0.0) sel(8) m1<1>UD g67<8,8,1>UD 0x3f800000UD { align1 1Q };
6 (+f0.0) sel(16) g2<1>UD g35<8,8,1>UD g41<8,8,1>UD { align1 1H };
7 (+f0.0) sel(16) m1<1>UD g31<8,8,1>UD 0x3f800000UD { align1 1H };
8 (+f0.0.all4h) sel(8) g45<1>UD g23<4>UD g24<4>UD { align16 1Q };
16 (+f0.0) sel(8) m1<1>UD g9<8,8,1>UD g12<8,8,1>UD { align1 1Q };
17 (+f0.0) sel(16) m1<1>UD g15<8,8,1>UD g21<8,8,1>UD { align1 1H };
[all …]
/external/mesa3d/src/intel/tools/tests/gen5/
Dsel.asm2 (-f0.0) sel(8) g2<1>UD g2<8,8,1>UD 0x00000000UD { align1 };
4 (-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
9 (+f0.0) sel(8) g2<1>UD g5<8,8,1>UD g6<8,8,1>UD { align1 };
10 (+f0.0) sel(8) m3<1>UD g4<8,8,1>UD g2<8,8,1>UD { align1 };
11 (+f0.0) sel(16) g4<1>UD g12<8,8,1>UD g14<8,8,1>UD { align1 compr };
12 (+f0.0) sel(16) m3<1>UD g10<8,8,1>UD g4<8,8,1>UD { align1 compr4 };
14 (+f0.0) sel(8) m7<1>UD g2<8,8,1>UD 0x3f000000UD { align1 };
15 (+f0.0) sel(16) m11<1>UD g4<8,8,1>UD 0x3f000000UD { align1 compr };
16 (+f0.0) sel(8) g15<1>UD g16<4>UD g15<4>UD { align16 };
21 (-f0.0) sel(8) m5<1>UD g2<8,8,1>UD 0x00000000UD { align1 };
[all …]
/external/igt-gpu-tools/lib/i915/shaders/ps/
Dneg1_test.g7a1 mov(8) g112:UD 0x3f800000:UD { align1 };
2 mov(8) g113:UD 0x3f800000:UD { align1 };
3 mov(8) g114:UD 0x3f800000:UD { align1 };
4 mov(8) g115:UD 0x3f800000:UD { align1 };
5 mov(8) g116:UD 0x3f800000:UD { align1 };
6 mov(8) g117:UD 0x3f800000:UD { align1 };
7 mov(8) g118:UD 0x3f800000:UD { align1 };
8 mov(8) g119:UD 0x3f800000:UD { align1 };

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