| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv7.txt | 341 # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
347 # A8.6.244 UMAAL
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| D | thumb2.txt | 2416 # UMAAL
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| D | basic-arm-instructions.txt | 2278 # UMAAL
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv7.txt | 364 # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
370 # A8.6.244 UMAAL
|
| D | basic-arm-instructions.txt | 2278 # UMAAL
|
| D | thumb2.txt | 2416 # UMAAL
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 168 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply enumerator
|
| D | ARMISelDAGToDAG.cpp | 2936 case ARMISD::UMAAL: { in Select()
2937 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
2970 unsigned opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
|
| D | ARMScheduleSwift.td | 293 "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB", "t2SMLALBT",
|
| D | ARMISelLowering.cpp | 1218 case ARMISD::UMAAL: return "ARMISD::UMAAL"; in getTargetNodeName()
9013 SDValue UMAAL = DAG.getNode(ARMISD::UMAAL, SDLoc(AddcNode), in AddCombineTo64bitUMAAL() local
9017 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), SDValue(UMAAL.getNode(), 1)); in AddCombineTo64bitUMAAL()
9018 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), SDValue(UMAAL.getNode(), 0)); in AddCombineTo64bitUMAAL()
|
| D | ARMScheduleA9.td | 2502 "UMAAL", "SMLALv5", "UMLALv5", "UMAALv5", "SMLALBB", "SMLALBT", "SMLALTB",
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 212 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply enumerator
|
| D | ARMScheduleR52.td | 281 "UMAAL", "t2SMLAL", "t2UMLAL",
|
| D | ARMScheduleSwift.td | 309 "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT",
|
| D | ARMISelDAGToDAG.cpp | 3380 case ARMISD::UMAAL: { in Select()
3381 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
|
| D | ARMISelLowering.cpp | 1655 case ARMISD::UMAAL: return "ARMISD::UMAAL"; in getTargetNodeName()
11574 SDValue UMAAL = DAG.getNode(ARMISD::UMAAL, SDLoc(AddcNode), in AddCombineTo64bitUMAAL() local
11578 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), SDValue(UMAAL.getNode(), 1)); in AddCombineTo64bitUMAAL()
11579 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), SDValue(UMAAL.getNode(), 0)); in AddCombineTo64bitUMAAL()
11601 return DAG.getNode(ARMISD::UMAAL, SDLoc(N), in PerformUMLALCombine()
|
| D | ARMScheduleA9.td | 2552 "UMAAL", "SMLALv5", "UMLALv5", "SMLALBB", "SMLALBT", "SMLALTB",
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 255 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply enumerator
|
| D | ARMScheduleR52.td | 281 "UMAAL", "t2SMLAL", "t2UMLAL",
|
| D | ARMScheduleSwift.td | 309 "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT",
|
| D | ARMISelDAGToDAG.cpp | 3586 case ARMISD::UMAAL: { in Select()
3587 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
|
| D | ARMISelLowering.cpp | 1754 case ARMISD::UMAAL: return "ARMISD::UMAAL"; in getTargetNodeName()
12021 SDValue UMAAL = DAG.getNode(ARMISD::UMAAL, SDLoc(AddcNode), in AddCombineTo64bitUMAAL() local
12025 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), SDValue(UMAAL.getNode(), 1)); in AddCombineTo64bitUMAAL()
12026 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), SDValue(UMAAL.getNode(), 0)); in AddCombineTo64bitUMAAL()
12048 return DAG.getNode(ARMISD::UMAAL, SDLoc(N), in PerformUMLALCombine()
|
| D | ARMScheduleA9.td | 2552 "UMAAL", "SMLALv5", "UMLALv5", "SMLALBB", "SMLALBT", "SMLALTB",
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 2562 3264039U, // UMAAL
6786 33554432U, // UMAAL
11450 case ARM::UMAAL:
11554 case ARM::UMAAL:
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 3315 @ UMAAL
|