| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | misched-int-basic.mir | 61 # CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr(tied-def 0), …
123 %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg
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| /external/llvm-project/llvm/test/MC/ARM/ |
| D | mul-v4.s | 1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
|
| /external/llvm/test/MC/ARM/ |
| D | mul-v4.s | 1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 166 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
|
| D | ARMScheduleSwift.td | 291 (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
|
| D | ARMISelDAGToDAG.cpp | 2945 case ARMISD::UMLAL:{ in Select()
2990 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
|
| D | ARMInstrInfo.td | 3944 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3975 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
5780 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5794 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
|
| D | ARMISelLowering.cpp | 1219 case ARMISD::UMLAL: return "ARMISD::UMLAL"; in getTargetNodeName()
8891 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
8979 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
8982 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 223 TmpInst.setOpcode(ARM::UMLAL);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 210 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
|
| D | ARMScheduleR52.td | 279 "SMLAL", "UMLAL", "SMLALBT",
|
| D | ARMScheduleSwift.td | 307 (instregex "SMLAL", "UMLAL", "SMLALBT",
|
| D | ARMISelDAGToDAG.cpp | 3389 case ARMISD::UMLAL:{ in Select()
3403 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
|
| D | ARMInstrInfo.td | 4205 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4239 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
6178 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6192 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 253 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
|
| D | ARMScheduleR52.td | 279 "SMLAL", "UMLAL", "SMLALBT",
|
| D | ARMScheduleSwift.td | 307 (instregex "SMLAL", "UMLAL", "SMLALBT",
|
| D | ARMInstrInfo.td | 4355 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4389 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
6335 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6349 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
|
| D | ARMISelDAGToDAG.cpp | 3595 case ARMISD::UMLAL:{ in Select()
3609 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 525 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 524 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 523 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
|
| /external/capstone/arch/ARM/ |
| D | ARMGenAsmWriter.inc | 518 92196U, // UMLAL
3322 0U, // UMLAL
6207 // SMLAL, UMLAL
9265 // (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 5842 ### UMLAL ### subsection
5852 ### UMLAL ### subsection
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 2288 # UMLAL
|