| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-mul-div-cte.ll | 47 ; CHECK-NEXT: umull [[UMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b
48 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).16b]], [[UMULL]].16b, [[UMULL2]].16b
59 ; CHECK-NEXT: umull [[UMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h
60 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).8h]], [[UMULL]].8h, [[SMULL2]].8h
74 ; CHECK-NEXT: umull [[UMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s
75 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).4s]], [[UMULL]].4s, [[SMULL2]].4s
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | mcp-dest-regs-no-dup.mir | 8 …dead renamable $r9, renamable $r0 = UMULL renamable $lr, killed renamable $r0, 14 /* CC::al */, $n…
10 …; CHECK: dead renamable $r9, renamable $r0 = UMULL renamable $lr, killed renamable $r0, 14 /* CC::…
|
| D | misched-int-basic.mir | 56 # CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, $noreg, $noreg
119 %7, %8 = UMULL %6, %6, 14, $noreg, $noreg
120 %13, %10 = UMULL %7, %7, 14, $noreg, $noreg
|
| D | 2011-02-04-AntidepMultidef.ll | 2 ; rdar://8959122 illegal register operands for UMULL instruction
|
| /external/libxaac/decoder/armv8/ |
| D | ixheaacd_overlap_add2.s | 78 UMULL V23.4S, V0.4H, V2.4H
96 UMULL V19.4S, V8.4H, V10.4H
100 UMULL V23.4S, V0.4H, V2.4H
143 UMULL V19.4S, V8.4H, V10.4H
198 UMULL V23.4S, V1.4H, V3.4H
209 UMULL V23.4S, V1.4H, V3.4H
234 UMULL V19.4S, V9.4H, V11.4H
248 UMULL V23.4S, V1.4H, V3.4H
286 UMULL V19.4S, V9.4H, V11.4H
|
| D | ixheaacd_overlap_add1.s | 95 UMULL V15.4S, V7.4H, V2.4H
114 UMULL V12.4S, V31.4H, V3.4H
153 UMULL V15.4S, V7.4H, V2.4H
155 UMULL V12.4S, V1.4H, V3.4H
206 UMULL V15.4S, V7.4H, V2.4H
211 UMULL V12.4S, V1.4H, V3.4H
274 UMULL V15.4S, V7.4H, V2.4H
276 UMULL V12.4s, V1.4H, V3.4H
|
| D | ixheaacd_sbr_imdct_using_fft.s | 284 UMULL V19.4S, V26.4H, V31.4H
285 UMULL V18.4S, V28.4H, V31.4H
292 UMULL V13.4S, V24.4H, V31.4H
293 UMULL V14.4S, V22.4H, V31.4H
|
| D | ixheaacd_imdct_using_fft.s | 331 UMULL v19.4S, v26.4H, v31.4H
332 UMULL v18.4S, v28.4H, v31.4H
341 UMULL v13.4S, v24.4H, v31.4H
342 UMULL v14.4S, v22.4H, v31.4H
|
| /external/llvm/test/CodeGen/ARM/ |
| D | 2011-02-04-AntidepMultidef.ll | 2 ; rdar://8959122 illegal register operands for UMULL instruction
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | etmv3_0x12.txt | 202 Instruction 186 S:0xC0011404 0xFBA02304 3 UMULL r2,r3,r0,r4 false
329 Instruction 313 S:0xC003BC7A 0xFBA8890C 1 UMULL r8,r9,r8,r12 false
479 Instruction 463 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
481 Instruction 465 S:0xC003F978 0xFBA06706 1 UMULL r6,r7,r0,r6 false
579 Instruction 563 S:0xC0043184 0xFBAE2305 2 UMULL r2,r3,lr,r5 false
580 Instruction 564 S:0xC0043188 0xFBAE4504 1 UMULL r4,r5,lr,r4 false
586 Instruction 570 S:0xC004319E 0xFBA22303 3 UMULL r2,r3,r2,r3 false
623 Instruction 607 S:0xC00431EA 0xFBA8230E 2 UMULL r2,r3,r8,lr false
732 Instruction 712 S:0xC003FC18 0xFBAC8906 3 UMULL r8,r9,r12,r6 false
798 Instruction 778 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
[all …]
|
| D | etmv3_0x10.txt | 70 Instruction 61 S:0xC004EFFE 0xFBA86702 1 UMULL r6,r7,r8,r2 false
237 Instruction 215 S:0xC004EFFE 0xFBA86702 1 UMULL r6,r7,r8,r2 false
523 Instruction 487 S:0xC00202DC 0xFBA32000 2 UMULL r2,r0,r3,r0 false
909 Instruction 848 S:0xC004EFFE 0xFBA86702 1 UMULL r6,r7,r8,r2 false
1454 Instruction 1332 S:0xC0011404 0xFBA02304 3 UMULL r2,r3,r0,r4 false
1648 Instruction 1526 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
1650 Instruction 1528 S:0xC003F978 0xFBA06706 1 UMULL r6,r7,r0,r6 false
1754 Instruction 1632 S:0xC00427FC 0xFBA02301 3 UMULL r2,r3,r0,r1 false
1758 Instruction 1636 S:0xC0042806 0xFBA10100 3 UMULL r0,r1,r1,r0 false
1765 Instruction 1643 S:0xC0042820 0xFBA22303 10 UMULL r2,r3,r2,r3 false
[all …]
|
| D | etmv3_0x11.txt | 830 Instruction 800 S:0xC0011404 0xFBA02304 3 UMULL r2,r3,r0,r4 false
1042 Instruction 1012 S:0xC0043ED2 0xFBA50102 1 UMULL r0,r1,r5,r2 false
1043 Instruction 1013 S:0xC0043ED6 0xFBA42302 1 UMULL r2,r3,r4,r2 false
1152 Instruction 1122 S:0xC0044028 0xFBA02301 1 UMULL r2,r3,r0,r1 false
1153 Instruction 1123 S:0xC004402C 0xFBA00104 1 UMULL r0,r1,r0,r4 false
1158 Instruction 1128 S:0xC004403E 0xFBA2230E 3 UMULL r2,r3,r2,lr false
1193 Instruction 1163 S:0xC0044090 0xFBA52303 1 UMULL r2,r3,r5,r3 false
1293 Instruction 1259 S:0xC003FC18 0xFBAC8906 3 UMULL r8,r9,r12,r6 false
1541 Instruction 1505 S:0xC003F970 0xFBA18906 3 UMULL r8,r9,r1,r6 false
1543 Instruction 1507 S:0xC003F978 0xFBA06706 1 UMULL r6,r7,r0,r6 false
[all …]
|
| D | ptmv1_0x13.txt | 221 Instruction 196 S:0xC004F5B4 0xFBA0230C 0 UMULL r2,r3,r0,r12 false
344 Instruction 317 S:0xC004F5B4 0xFBA0230C 0 UMULL r2,r3,r0,r12 false
400 Instruction 373 S:0xC00542D2 0xFBA64503 0 UMULL r4,r5,r6,r3 false
1147 Instruction 1081 S:0xC004EFFE 0xFBA86702 0 UMULL r6,r7,r8,r2 false
1363 Instruction 1291 S:0xC004F5B4 0xFBA0230C 0 UMULL r2,r3,r0,r12 false
1604 Instruction 1528 S:0xC0011404 0xFBA02304 0 UMULL r2,r3,r0,r4 false
1707 Instruction 1631 S:0xC004463C 0xFBA22304 0 UMULL r2,r3,r2,r4 false
1748 Instruction 1672 S:0xC0043ED2 0xFBA50102 0 UMULL r0,r1,r5,r2 false
1749 Instruction 1673 S:0xC0043ED6 0xFBA42302 0 UMULL r2,r3,r4,r2 false
1864 Instruction 1787 S:0xC0044DBE 0xFBA22301 0 UMULL r2,r3,r2,r1 false
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 188 UMULL, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 256 TmpInst.setOpcode(ARM::UMULL);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 196 UMULL, enumerator
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 276 UMULL, enumerator
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_32.c | 110 #define UMULL 0xe0800090 macro
1705 return push_inst(compiler, (op == SLJIT_LMUL_UW ? UMULL : SMULL) in sljit_emit_op0()
|
| D | sljitNativeARM_T2_32.c | 179 #define UMULL 0xfba00000 macro
1263 return push_inst32(compiler, (op == SLJIT_LMUL_UW ? UMULL : SMULL) in sljit_emit_op0()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 278 "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$",
|
| D | ARMScheduleSwift.td | 281 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 277 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 278 "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$",
|
| D | ARMScheduleSwift.td | 281 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3158 ### UMULL ### subsection
5917 ### UMULL ### subsection
5927 ### UMULL ### subsection
|