| /external/llvm-project/llvm/test/CodeGen/WebAssembly/ |
| D | umulo-i64.ll | 2 ; Test that UMULO works correctly on 64-bit operands.
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 238 SMULO, UMULO, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 258 SMULO, UMULO, enumerator
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 312 UMULO, enumerator
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| D | SelectionDAGNodes.h | 2729 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 233 case ISD::UMULO: return "umulo"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 137 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
786 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1401 case ISD::UMULO: in ExpandIntegerResult()
2548 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 324 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break; in mightUseCTR()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 450 case ISD::UMULO: in LegalizeOp()
832 case ISD::UMULO: in Expand()
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| D | SelectionDAGDumper.cpp | 302 case ISD::UMULO: return "umulo"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 148 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
1346 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
2135 case ISD::UMULO: in ExpandIntegerResult()
3372 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
3883 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
3910 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow); in ExpandIntRes_XMULO()
3915 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow); in ExpandIntRes_XMULO()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 146 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
1153 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1903 case ISD::UMULO: in ExpandIntegerResult()
3040 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
3518 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
3545 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow); in ExpandIntRes_XMULO()
3550 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow); in ExpandIntRes_XMULO()
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| D | SelectionDAGDumper.cpp | 297 case ISD::UMULO: return "umulo"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 453 case ISD::UMULO: in LegalizeOp()
942 case ISD::UMULO: in Expand()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 531 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break; in mightUseCTR()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2678 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto in getTypeBasedIntrinsicInstrCost()
2701 { ISD::UMULO, MVT::i32, 2 }, // mul + seto in getTypeBasedIntrinsicInstrCost()
2702 { ISD::UMULO, MVT::i16, 2 }, in getTypeBasedIntrinsicInstrCost()
2703 { ISD::UMULO, MVT::i8, 2 }, in getTypeBasedIntrinsicInstrCost()
2778 ISD = ISD::UMULO; in getTypeBasedIntrinsicInstrCost()
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| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1681 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2942 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3062 case ISD::UMULO: in LowerOperation()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1707 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2961 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3081 case ISD::UMULO: in LowerOperation()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1674 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2936 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3056 case ISD::UMULO: in LowerOperation()
|
| /external/llvm/test/CodeGen/X86/ |
| D | xaluo.ll | 344 ; UMULO
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 670 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 884 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 249 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
250 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
1645 case ISD::UMULO: { in getAArch64XALUOOp()
2347 case ISD::UMULO: in LowerOperation()
3639 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerBR_CC()
4088 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerSELECT()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 784 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | xmulo.ll | 138 ; UMULO
|