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Searched refs:UNINDEXED (Results 1 – 25 of 53) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h2211 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2214 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2315 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2318 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2606 Ld->getAddressingMode() == ISD::UNINDEXED;
2636 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2644 St->getAddressingMode() == ISD::UNINDEXED;
2660 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
DISDOpcodes.h986 UNINDEXED = 0, enumerator
DBasicTTIImpl.h177 return ISD::UNINDEXED; in getISDIndexedMode()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h808 UNINDEXED = 0, enumerator
DSelectionDAGNodes.h1798 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
1801 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2085 Ld->getAddressingMode() == ISD::UNINDEXED;
2115 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2123 St->getAddressingMode() == ISD::UNINDEXED;
2139 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/llvm-project/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h2226 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2229 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2327 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2330 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2650 Ld->getAddressingMode() == ISD::UNINDEXED;
2680 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2688 St->getAddressingMode() == ISD::UNINDEXED;
2704 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
DISDOpcodes.h1212 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
DBasicTTIImpl.h174 return ISD::UNINDEXED; in getISDIndexedMode()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp523 if (AM != ISD::UNINDEXED) { in SelectLoad()
631 if (AM != ISD::UNINDEXED) { in SelectStore()
673 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
702 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp1843 Thru.first, SingleTy, MOp0, ISD::UNINDEXED, in SplitHvxMemOp()
1847 Thru.second, SingleTy, MOp1, ISD::UNINDEXED, in SplitHvxMemOp()
1858 ISD::UNINDEXED, false, false); in SplitHvxMemOp()
1861 ISD::UNINDEXED, false, false); in SplitHvxMemOp()
1896 ISD::UNINDEXED, ISD::NON_EXTLOAD, false); in WidenHvxLoad()
1932 MemOp, ISD::UNINDEXED, false, false); in WidenHvxStore()
DHexagonISelDAGToDAG.cpp452 if (AM != ISD::UNINDEXED) { in SelectLoad()
561 if (AM != ISD::UNINDEXED) { in SelectStore()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp5105 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
5138 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
5146 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
5157 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
5166 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
5218 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(), in getStore()
5227 ISD::UNINDEXED, false, VT, MMO); in getStore()
5288 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(), in getTruncStore()
5297 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
5341 ID.AddInteger(encodeMemSDNodeFlags(ExtTy, ISD::UNINDEXED, in getMaskedLoad()
[all …]
DLegalizeVectorTypes.cpp226 SDValue Result = DAG.getLoad(ISD::UNINDEXED, in ScalarizeVecRes_LOAD()
1063 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1070 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
DTargetLowering.cpp3245 assert(LD->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedLoad()
3402 assert(ST->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedStore()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp6843 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
6877 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
6884 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
6895 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, PtrInfo, in getExtLoad()
6903 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
6955 dl.getIROrder(), VTs, ISD::UNINDEXED, false, VT, MMO)); in getStore()
6963 ISD::UNINDEXED, false, VT, MMO); in getStore()
7022 dl.getIROrder(), VTs, ISD::UNINDEXED, true, SVT, MMO)); in getTruncStore()
7030 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
7074 bool Indexed = AM != ISD::UNINDEXED; in getMaskedLoad()
[all …]
DLegalizeVectorTypes.cpp330 ISD::UNINDEXED, N->getExtensionType(), in ScalarizeVecRes_LOAD()
1512 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1517 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp6979 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
7013 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
7020 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
7031 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, PtrInfo, in getExtLoad()
7039 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
7090 dl.getIROrder(), VTs, ISD::UNINDEXED, false, VT, MMO)); in getStore()
7098 ISD::UNINDEXED, false, VT, MMO); in getStore()
7156 dl.getIROrder(), VTs, ISD::UNINDEXED, true, SVT, MMO)); in getTruncStore()
7164 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
7208 bool Indexed = AM != ISD::UNINDEXED; in getMaskedLoad()
[all …]
DLegalizeVectorTypes.cpp343 ISD::UNINDEXED, N->getExtensionType(), in ScalarizeVecRes_LOAD()
1632 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1639 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI, in SplitVecRes_LOAD()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td709 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
819 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp452 if (AM != ISD::UNINDEXED) { in SelectLoad()
561 if (AM != ISD::UNINDEXED) { in SelectStore()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1524 if (AM == ISD::UNINDEXED) in tryARMIndexedLoad()
1630 if (AM == ISD::UNINDEXED) in tryT2IndexedLoad()
1689 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
1705 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1571 if (AM == ISD::UNINDEXED) in tryARMIndexedLoad()
1677 if (AM == ISD::UNINDEXED) in tryT2IndexedLoad()
1736 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
1752 if (AM == ISD::UNINDEXED) in tryMVEIndexedLoad()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td777 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
778 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td775 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
776 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1474 if (AM == ISD::UNINDEXED) in tryARMIndexedLoad()
1549 if (AM == ISD::UNINDEXED) in tryT2IndexedLoad()

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