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Searched refs:USUBSAT (Results 1 – 25 of 40) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-usubsat.mir33 ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
34 ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
45 ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
46 ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
85 ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
86 ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
97 ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
98 ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
171 ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
172 ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C3]](s16)
[all …]
Dirtranslator-sat.ll171 ; CHECK: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]]
172 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16)
188 ; CHECK: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]]
189 ; CHECK: $vgpr0 = COPY [[USUBSAT]](s32)
208 ; CHECK: [[USUBSAT:%[0-9]+]]:_(s64) = G_USUBSAT [[MV]], [[MV1]]
209 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](s64)
230 ; CHECK: [[USUBSAT:%[0-9]+]]:_(<2 x s32>) = G_USUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
231 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](<2 x s32>)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1932 { ISD::USUBSAT, MVT::v32i16, 1 }, in getIntrinsicInstrCost()
1933 { ISD::USUBSAT, MVT::v64i8, 1 }, in getIntrinsicInstrCost()
1944 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd in getIntrinsicInstrCost()
1945 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq in getIntrinsicInstrCost()
1946 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq in getIntrinsicInstrCost()
1947 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq in getIntrinsicInstrCost()
1994 { ISD::USUBSAT, MVT::v16i16, 1 }, in getIntrinsicInstrCost()
1995 { ISD::USUBSAT, MVT::v32i8, 1 }, in getIntrinsicInstrCost()
1996 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd in getIntrinsicInstrCost()
2031 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getIntrinsicInstrCost()
[all …]
DX86ISelLowering.cpp911 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal); in X86TargetLowering()
915 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal); in X86TargetLowering()
918 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom); in X86TargetLowering()
920 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom); in X86TargetLowering()
1291 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1295 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1426 setOperationAction(ISD::USUBSAT, VT, Custom); in X86TargetLowering()
1739 setOperationAction(ISD::USUBSAT, VT, Custom); in X86TargetLowering()
1823 setOperationAction(ISD::USUBSAT, VT, Legal); in X86TargetLowering()
21346 SDValue Result = DAG.getNode(ISD::USUBSAT, dl, VT, Op0, Op1); in LowerVSETCCWithSUBUS()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h274 SSUBSAT, USUBSAT, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h330 USUBSAT, enumerator
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp2341 { ISD::USUBSAT, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2342 { ISD::USUBSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2391 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd in getTypeBasedIntrinsicInstrCost()
2392 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq in getTypeBasedIntrinsicInstrCost()
2393 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq in getTypeBasedIntrinsicInstrCost()
2394 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq in getTypeBasedIntrinsicInstrCost()
2405 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2406 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2473 { ISD::USUBSAT, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2474 { ISD::USUBSAT, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp455 case ISD::USUBSAT: in LegalizeOp()
836 case ISD::USUBSAT: in Expand()
DSelectionDAGDumper.cpp314 case ISD::USUBSAT: return "usubsat"; in getOperationName()
DTargetLowering.cpp7505 isOperationLegal(ISD::USUBSAT, VT)) { in expandIntMINMAX()
7507 DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1)); in expandIntMINMAX()
7512 isOperationLegal(ISD::USUBSAT, VT)) { in expandIntMINMAX()
7514 DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0)); in expandIntMINMAX()
7547 if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) { in expandAddSubSat()
7570 case ISD::USUBSAT: in expandAddSubSat()
7600 } else if (Opcode == ISD::USUBSAT) { in expandAddSubSat()
DLegalizeIntegerTypes.cpp161 case ISD::USUBSAT: in PromoteIntegerResult()
744 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSHLSAT()
765 case ISD::USUBSAT: in PromoteIntRes_ADDSUBSHLSAT()
787 if (Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSHLSAT()
2141 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break; in ExpandIntegerResult()
DLegalizeVectorTypes.cpp131 case ISD::USUBSAT: in ScalarizeVectorResult()
999 case ISD::USUBSAT: in SplitVectorResult()
2889 case ISD::USUBSAT: in WidenVectorResult()
DSelectionDAG.cpp4802 case ISD::USUBSAT: return C1.usub_sat(C2); in FoldValue()
5264 case ISD::USUBSAT: in getNode()
5574 case ISD::USUBSAT: in getNode()
5599 case ISD::USUBSAT: in getNode()
DLegalizeDAG.cpp1137 case ISD::USUBSAT: in LegalizeOp()
3546 case ISD::USUBSAT: in ExpandNode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp308 case ISD::USUBSAT: return "usubsat"; in getOperationName()
DLegalizeVectorOps.cpp458 case ISD::USUBSAT: in LegalizeOp()
946 case ISD::USUBSAT: in Expand()
DLegalizeIntegerTypes.cpp156 case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break; in PromoteIntegerResult()
681 if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSAT()
699 case ISD::USUBSAT: in PromoteIntRes_ADDSUBSAT()
719 if (Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSAT()
1909 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break; in ExpandIntegerResult()
DLegalizeVectorTypes.cpp128 case ISD::USUBSAT: in ScalarizeVectorResult()
938 case ISD::USUBSAT: in SplitVectorResult()
2729 case ISD::USUBSAT: in WidenVectorResult()
DSelectionDAG.cpp4809 case ISD::USUBSAT: return C1.usub_sat(C2); in FoldValue()
5206 case ISD::USUBSAT: in getNode()
5475 case ISD::USUBSAT: in getNode()
5500 case ISD::USUBSAT: in getNode()
DTargetLowering.cpp7103 if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) { in expandAddSubSat()
7125 case ISD::USUBSAT: in expandAddSubSat()
7150 } else if (Opcode == ISD::USUBSAT) { in expandAddSubSat()
DLegalizeDAG.cpp1125 case ISD::USUBSAT: { in LegalizeOp()
3413 case ISD::USUBSAT: in ExpandNode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp656 setOperationAction(ISD::USUBSAT, VT, Expand); in initActions()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp766 setOperationAction(ISD::USUBSAT, VT, Expand); in initActions()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp494 setOperationAction(ISD::USUBSAT, MVT::i32, Legal); in SITargetLowering()
557 setOperationAction(ISD::USUBSAT, MVT::i16, Legal); in SITargetLowering()
723 setOperationAction(ISD::USUBSAT, MVT::v2i16, Legal); in SITargetLowering()
756 setOperationAction(ISD::USUBSAT, MVT::v4i16, Custom); in SITargetLowering()
4586 case ISD::USUBSAT: in LowerOperation()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td397 def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>;

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