| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 41 UXTH, enumerator
61 case AArch64_AM::UXTH: return "uxth"; in getShiftExtendName()
128 case 1: return AArch64_AM::UXTH; in getExtendType()
155 case AArch64_AM::UXTH: return 1; break; in getExtendEncoding()
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | misched-int-basic.mir | 41 # CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, $noreg
116 %4 = UXTH %3, 0, 14, $noreg
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 41 UXTH, enumerator
61 case AArch64_AM::UXTH: return "uxth"; in getShiftExtendName()
128 case 1: return AArch64_AM::UXTH; in getExtendType()
155 case AArch64_AM::UXTH: return 1; break; in getExtendEncoding()
|
| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 41 UXTH, enumerator
61 case AArch64_AM::UXTH: return "uxth"; in getShiftExtendName()
128 case 1: return AArch64_AM::UXTH; in getExtendType()
155 case AArch64_AM::UXTH: return 1; break; in getExtendEncoding()
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-t32.json | 62 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> ; T1
63 // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-ror-amount-a32.json | 37 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| D | cond-rd-operand-rn-ror-amount-t32.json | 37 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-a32.json | 51 "Uxth" // UXTH{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 521 # UXTB/UXTH
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 521 # UXTB/UXTH
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 360 UXTH, enumerator
|
| /external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/ |
| D | arm-instruction-select.mir | 171 ; CHECK: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14 /* CC::al */, $noreg
172 ; CHECK: $r0 = COPY [[UXTH]]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 458 UXTH, enumerator
|
| /external/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 458 UXTH, enumerator
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-intrinsics-conversion.ll | 114 ; UXTH
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredicates.td | 19 def CheckExtUXTH : CheckImmOperand_s<3, "AArch64_AM::UXTH">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredicates.td | 19 def CheckExtUXTH : CheckImmOperand_s<3, "AArch64_AM::UXTH">;
|
| D | AArch64ExpandPseudoInsts.cpp | 642 AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0), in expandMI()
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_post_twiddle_overlap.s | 133 UXTH R5, R10, ROR #16
134 UXTH R10, R10
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 329 COMPARE(add(w6, w7, Operand(w8, UXTH, 2)), "add w6, w7, w8, uxth #2"); in TEST()
341 COMPARE(add(x2, sp, Operand(x3, UXTH, 1)), "add x2, sp, w3, uxth #1"); in TEST()
355 COMPARE(sub(w6, w7, Operand(w8, UXTH, 2)), "sub w6, w7, w8, uxth #2"); in TEST()
364 COMPARE(cmp(x2, Operand(x3, UXTH, 3)), "cmp x2, w3, uxth #3"); in TEST()
367 COMPARE(sub(x2, sp, Operand(x3, UXTH, 1)), "sub x2, sp, w3, uxth #1"); in TEST()
|
| D | test-assembler-aarch64.cc | 190 __ Mvn(w12, Operand(w2, UXTH, 2)); in TEST()
364 __ Mov(w25, Operand(w13, UXTH, 2)); in TEST()
418 __ Mov(w21, Operand(w11, UXTH, 1)); in TEST()
425 __ Mov(x27, Operand(x12, UXTH, 1)); in TEST()
498 __ Orr(x7, x0, Operand(x1, UXTH, 1)); in TEST()
592 __ Orn(x7, x0, Operand(x1, UXTH, 1)); in TEST()
659 __ And(x7, x0, Operand(x1, UXTH, 1)); in TEST()
805 __ Bic(x7, x0, Operand(x1, UXTH, 1)); in TEST()
937 __ Eor(x7, x0, Operand(x1, UXTH, 1)); in TEST()
1004 __ Eon(x7, x0, Operand(x1, UXTH, 1)); in TEST()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 913 AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0), in expandMI()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 301 STORE_OPCODE(ZEXT16, UXTH); in OpcodeCache()
|