Home
last modified time | relevance | path

Searched refs:UseI (Results 1 – 25 of 40) sorted by relevance

12

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64StackTaggingPreRA.cpp176 MachineInstr *UseI = &*(UI++); in uncheckUsesOf() local
177 if (isUncheckedLoadOrStoreOpcode(UseI->getOpcode())) { in uncheckUsesOf()
179 unsigned OpIdx = TII->getLoadStoreImmIdx(UseI->getOpcode()) - 1; in uncheckUsesOf()
180 if (UseI->getOperand(OpIdx).isReg() && in uncheckUsesOf()
181 UseI->getOperand(OpIdx).getReg() == TaggedReg) { in uncheckUsesOf()
182 UseI->getOperand(OpIdx).ChangeToFrameIndex(FI); in uncheckUsesOf()
183 UseI->getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED); in uncheckUsesOf()
185 } else if (UseI->isCopy() && in uncheckUsesOf()
186 Register::isVirtualRegister(UseI->getOperand(0).getReg())) { in uncheckUsesOf()
187 uncheckUsesOf(UseI->getOperand(0).getReg(), FI); in uncheckUsesOf()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64StackTaggingPreRA.cpp182 MachineInstr *UseI = &*(UI++); in uncheckUsesOf() local
183 if (isUncheckedLoadOrStoreOpcode(UseI->getOpcode())) { in uncheckUsesOf()
185 unsigned OpIdx = TII->getLoadStoreImmIdx(UseI->getOpcode()) - 1; in uncheckUsesOf()
186 if (UseI->getOperand(OpIdx).isReg() && in uncheckUsesOf()
187 UseI->getOperand(OpIdx).getReg() == TaggedReg) { in uncheckUsesOf()
188 UseI->getOperand(OpIdx).ChangeToFrameIndex(FI); in uncheckUsesOf()
189 UseI->getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED); in uncheckUsesOf()
191 } else if (UseI->isCopy() && in uncheckUsesOf()
192 Register::isVirtualRegister(UseI->getOperand(0).getReg())) { in uncheckUsesOf()
193 uncheckUsesOf(UseI->getOperand(0).getReg(), FI); in uncheckUsesOf()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600EmitClauseMarkers.cpp198 for (MachineBasicBlock::iterator UseI = Def; UseI != BBEnd; ++UseI) { in canClauseLocalKillFitInClause() local
199 AluInstCount += OccupiedDwords(*UseI); in canClauseLocalKillFitInClause()
201 if (!SubstituteKCacheBank(*UseI, KCacheBanks, false)) in canClauseLocalKillFitInClause()
215 if (UseI->findRegisterUseOperandIdx(MOI->getReg())) in canClauseLocalKillFitInClause()
218 if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1) in canClauseLocalKillFitInClause()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600EmitClauseMarkers.cpp210 for (MachineBasicBlock::iterator UseI = Def; UseI != BBEnd; ++UseI) { in canClauseLocalKillFitInClause() local
211 AluInstCount += OccupiedDwords(*UseI); in canClauseLocalKillFitInClause()
213 if (!SubstituteKCacheBank(*UseI, KCacheBanks, false)) in canClauseLocalKillFitInClause()
228 if (UseI->readsRegister(MOI->getReg(), &TRI)) in canClauseLocalKillFitInClause()
232 if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI)) in canClauseLocalKillFitInClause()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600EmitClauseMarkers.cpp210 for (MachineBasicBlock::iterator UseI = Def; UseI != BBEnd; ++UseI) { in canClauseLocalKillFitInClause() local
211 AluInstCount += OccupiedDwords(*UseI); in canClauseLocalKillFitInClause()
213 if (!SubstituteKCacheBank(*UseI, KCacheBanks, false)) in canClauseLocalKillFitInClause()
228 if (UseI->readsRegister(MOI->getReg(), &TRI)) in canClauseLocalKillFitInClause()
232 if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI)) in canClauseLocalKillFitInClause()
DAMDGPUSubtarget.cpp769 MachineInstr *UseI = Use->getInstr(); in adjustSchedDependency() local
784 } else if (UseI->isBundle()) { in adjustSchedDependency()
787 MachineBasicBlock::const_instr_iterator I(UseI->getIterator()); in adjustSchedDependency()
788 MachineBasicBlock::const_instr_iterator E(UseI->getParent()->instr_end()); in adjustSchedDependency()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMIRCanonicalizerPass.cpp243 MachineBasicBlock::iterator UseI = BBE; in rescheduleCanonically() local
247 if (DefI != BBE && UseI != BBE) in rescheduleCanonically()
256 UseI = BBI; in rescheduleCanonically()
261 if (DefI == BBE || UseI == BBE) in rescheduleCanonically()
268 UseI->dump(); in rescheduleCanonically()
273 MBB->splice(UseI, MBB, DefI); in rescheduleCanonically()
279 auto UseI = in rescheduleCanonically() local
283 if (UseI == MBB->instr_end()) in rescheduleCanonically()
290 [&]() -> MachineBasicBlock::iterator { return UseI; }); in rescheduleCanonically()
DMachineCopyPropagation.cpp284 const MachineInstr &UseI, unsigned UseIdx);
286 const MachineInstr &UseI,
386 const MachineInstr &Copy, const MachineInstr &UseI, unsigned UseIdx) { in isBackwardPropagatableRegClassCopy() argument
390 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isBackwardPropagatableRegClassCopy()
402 const MachineInstr &UseI, in isForwardableRegClassCopy() argument
410 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
413 if (!UseI.isCopy()) in isForwardableRegClassCopy()
433 TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg()); in isForwardableRegClassCopy()
/external/llvm-project/llvm/lib/CodeGen/
DMIRCanonicalizerPass.cpp242 MachineBasicBlock::iterator UseI = BBE; in rescheduleCanonically() local
246 if (DefI != BBE && UseI != BBE) in rescheduleCanonically()
255 UseI = BBI; in rescheduleCanonically()
260 if (DefI == BBE || UseI == BBE) in rescheduleCanonically()
267 UseI->dump(); in rescheduleCanonically()
272 MBB->splice(UseI, MBB, DefI); in rescheduleCanonically()
278 auto UseI = in rescheduleCanonically() local
282 if (UseI == MBB->instr_end()) in rescheduleCanonically()
289 [&]() -> MachineBasicBlock::iterator { return UseI; }); in rescheduleCanonically()
DMachineCopyPropagation.cpp285 const MachineInstr &UseI, unsigned UseIdx);
287 const MachineInstr &UseI,
387 const MachineInstr &Copy, const MachineInstr &UseI, unsigned UseIdx) { in isBackwardPropagatableRegClassCopy() argument
391 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isBackwardPropagatableRegClassCopy()
403 const MachineInstr &UseI, in isForwardableRegClassCopy() argument
411 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
414 if (!UseI.isCopy()) in isForwardableRegClassCopy()
434 TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg()); in isForwardableRegClassCopy()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp253 MachineInstr *UseI = Op.getParent(); in partitionRegisters() local
254 if (isFixedInstr(UseI)) in partitionRegisters()
256 for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) { in partitionRegisters()
257 MachineOperand &MO = UseI->getOperand(i); in partitionRegisters()
438 MachineInstr *UseI = U->getParent(); in isProfitable() local
439 if (isFixedInstr(UseI)) { in isProfitable()
442 for (auto &Op : UseI->operands()) { in isProfitable()
453 if (UseI->isPHI()) { in isProfitable()
454 const MachineBasicBlock *PB = UseI->getParent(); in isProfitable()
460 int32_t P = profit(UseI); in isProfitable()
[all …]
DBitTracker.cpp987 for (MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) in visitUsesOf()
988 UseQ.push(&UseI); in visitUsesOf()
1106 MachineInstr &UseI = *UseQ.front(); in runUseQueue() local
1109 if (!InstrExec.count(&UseI)) in runUseQueue()
1111 if (UseI.isPHI()) in runUseQueue()
1112 visitPHI(UseI); in runUseQueue()
1113 else if (!UseI.isBranch()) in runUseQueue()
1114 visitNonBranch(UseI); in runUseQueue()
1116 visitBranchesFrom(UseI); in runUseQueue()
DHexagonBitSimplify.cpp976 MachineInstr *UseI = I->getParent(); in isDead() local
977 if (UseI->isDebugValue()) in isDead()
979 if (UseI->isPHI()) { in isDead()
980 assert(!UseI->getOperand(0).getSubReg()); in isDead()
981 Register DR = UseI->getOperand(0).getReg(); in isDead()
1220 MachineInstr &UseI = *I->getParent(); in computeUsedBits() local
1221 if (UseI.isPHI() || UseI.isCopy()) { in computeUsedBits()
1222 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits()
1227 if (!computeUsedBits(UseI, I.getOperandNo(), Used, B)) in computeUsedBits()
3127 MachineInstr *UseI = UI->getParent(); in processLoop() local
[all …]
DHexagonLoopIdiomRecognition.cpp602 bool classifyInst(Instruction *UseI, ValueSeq &Early, ValueSeq &Late);
1202 bool PolynomialMultiplyRecognize::classifyInst(Instruction *UseI, in classifyInst() argument
1207 if (UseI->getOpcode() == Instruction::Select) { in classifyInst()
1208 Value *TV = UseI->getOperand(1), *FV = UseI->getOperand(2); in classifyInst()
1212 Early.insert(UseI); in classifyInst()
1216 Late.insert(UseI); in classifyInst()
1223 if (UseI->getNumOperands() == 0) in classifyInst()
1227 for (auto &I : UseI->operands()) { in classifyInst()
1248 Early.insert(UseI); in classifyInst()
1250 Late.insert(UseI); in classifyInst()
[all …]
DHexagonGenPredicate.cpp240 MachineInstr *UseI = I->getParent(); in processPredicateGPR() local
241 if (isConvertibleToPredForm(UseI)) in processPredicateGPR()
242 PUsers.insert(UseI); in processPredicateGPR()
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp231 MachineInstr *UseI = Op.getParent(); in partitionRegisters() local
232 if (isFixedInstr(UseI)) in partitionRegisters()
234 for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) { in partitionRegisters()
235 MachineOperand &MO = UseI->getOperand(i); in partitionRegisters()
392 MachineInstr *UseI = U->getParent(); in isProfitable() local
393 if (isFixedInstr(UseI)) { in isProfitable()
396 for (auto &Op : UseI->operands()) { in isProfitable()
407 if (UseI->isPHI()) { in isProfitable()
408 const MachineBasicBlock *PB = UseI->getParent(); in isProfitable()
415 int32_t P = profit(UseI); in isProfitable()
[all …]
DHexagonBitSimplify.cpp922 MachineInstr *UseI = I->getParent(); in isDead() local
923 if (UseI->isDebugValue()) in isDead()
925 if (UseI->isPHI()) { in isDead()
926 assert(!UseI->getOperand(0).getSubReg()); in isDead()
927 unsigned DR = UseI->getOperand(0).getReg(); in isDead()
1165 MachineInstr &UseI = *I->getParent(); in computeUsedBits() local
1166 if (UseI.isPHI() || UseI.isCopy()) { in computeUsedBits()
1167 unsigned DefR = UseI.getOperand(0).getReg(); in computeUsedBits()
1172 if (!computeUsedBits(UseI, I.getOperandNo(), Used, B)) in computeUsedBits()
2536 MachineInstr *UseI = UI->getParent(); in processLoop() local
[all …]
DBitTracker.cpp982 MachineInstr *UseI = I->getParent(); in visitUsesOf() local
983 if (!InstrExec.count(UseI)) in visitUsesOf()
985 if (UseI->isPHI()) in visitUsesOf()
986 visitPHI(*UseI); in visitUsesOf()
987 else if (!UseI->isBranch()) in visitUsesOf()
988 visitNonBranch(*UseI); in visitUsesOf()
990 visitBranchesFrom(*UseI); in visitUsesOf()
DHexagonGenPredicate.cpp217 MachineInstr *UseI = I->getParent(); in processPredicateGPR() local
218 if (isConvertibleToPredForm(UseI)) in processPredicateGPR()
219 PUsers.insert(UseI); in processPredicateGPR()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp253 MachineInstr *UseI = Op.getParent(); in partitionRegisters() local
254 if (isFixedInstr(UseI)) in partitionRegisters()
256 for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) { in partitionRegisters()
257 MachineOperand &MO = UseI->getOperand(i); in partitionRegisters()
438 MachineInstr *UseI = U->getParent(); in isProfitable() local
439 if (isFixedInstr(UseI)) { in isProfitable()
442 for (auto &Op : UseI->operands()) { in isProfitable()
453 if (UseI->isPHI()) { in isProfitable()
454 const MachineBasicBlock *PB = UseI->getParent(); in isProfitable()
460 int32_t P = profit(UseI); in isProfitable()
[all …]
DBitTracker.cpp985 for (MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) in visitUsesOf()
986 UseQ.push(&UseI); in visitUsesOf()
1104 MachineInstr &UseI = *UseQ.front(); in runUseQueue() local
1107 if (!InstrExec.count(&UseI)) in runUseQueue()
1109 if (UseI.isPHI()) in runUseQueue()
1110 visitPHI(UseI); in runUseQueue()
1111 else if (!UseI.isBranch()) in runUseQueue()
1112 visitNonBranch(UseI); in runUseQueue()
1114 visitBranchesFrom(UseI); in runUseQueue()
DHexagonBitSimplify.cpp975 MachineInstr *UseI = I->getParent(); in isDead() local
976 if (UseI->isDebugValue()) in isDead()
978 if (UseI->isPHI()) { in isDead()
979 assert(!UseI->getOperand(0).getSubReg()); in isDead()
980 Register DR = UseI->getOperand(0).getReg(); in isDead()
1219 MachineInstr &UseI = *I->getParent(); in computeUsedBits() local
1220 if (UseI.isPHI() || UseI.isCopy()) { in computeUsedBits()
1221 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits()
1226 if (!computeUsedBits(UseI, I.getOperandNo(), Used, B)) in computeUsedBits()
3117 MachineInstr *UseI = UI->getParent(); in processLoop() local
[all …]
DHexagonLoopIdiomRecognition.cpp583 bool classifyInst(Instruction *UseI, ValueSeq &Early, ValueSeq &Late);
1183 bool PolynomialMultiplyRecognize::classifyInst(Instruction *UseI, in classifyInst() argument
1188 if (UseI->getOpcode() == Instruction::Select) { in classifyInst()
1189 Value *TV = UseI->getOperand(1), *FV = UseI->getOperand(2); in classifyInst()
1193 Early.insert(UseI); in classifyInst()
1197 Late.insert(UseI); in classifyInst()
1204 if (UseI->getNumOperands() == 0) in classifyInst()
1208 for (auto &I : UseI->operands()) { in classifyInst()
1229 Early.insert(UseI); in classifyInst()
1231 Late.insert(UseI); in classifyInst()
[all …]
DHexagonGenPredicate.cpp239 MachineInstr *UseI = I->getParent(); in processPredicateGPR() local
240 if (isConvertibleToPredForm(UseI)) in processPredicateGPR()
241 PUsers.insert(UseI); in processPredicateGPR()
/external/llvm/lib/CodeGen/
DSplitKit.cpp195 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE; in calcLiveBlockInfo() local
196 UseI = UseSlots.begin(); in calcLiveBlockInfo()
211 if (UseI == UseE || *UseI >= Stop) { in calcLiveBlockInfo()
220 BI.FirstInstr = *UseI; in calcLiveBlockInfo()
222 do ++UseI; in calcLiveBlockInfo()
223 while (UseI != UseE && *UseI < Stop); in calcLiveBlockInfo()
224 BI.LastInstr = UseI[-1]; in calcLiveBlockInfo()

12