| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 99 BitVector ModifiedRegs, UsedRegs; member
1032 BitVector &UsedRegs, in trackRegDefsUses() argument
1049 UsedRegs.set(*AI); in trackRegDefsUses()
1114 UsedRegs.reset(); in findMatchingStore()
1141 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingStore()
1225 UsedRegs.reset(); in findMatchingInsn()
1279 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingInsn()
1289 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingInsn()
1297 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingInsn()
1306 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingInsn()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 101 DenseSet<unsigned int> &UsedRegs);
261 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
308 for (unsigned int U : UsedRegs) in classifyInstruction()
367 DenseSet<unsigned int> UsedRegs; in collectCallInfo() local
369 while ((Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs)) != in collectCallInfo()
416 UsedRegs.insert(Reg); in collectCallInfo()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 114 DenseSet<unsigned int> &UsedRegs);
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
344 for (unsigned int U : UsedRegs) in classifyInstruction()
409 DenseSet<unsigned int> UsedRegs; in collectCallInfo() local
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
458 UsedRegs.insert(Reg); in collectCallInfo()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 115 DenseSet<unsigned int> &UsedRegs);
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
344 for (unsigned int U : UsedRegs) in classifyInstruction()
409 DenseSet<unsigned int> UsedRegs; in collectCallInfo() local
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
458 UsedRegs.insert(Reg); in collectCallInfo()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInsertWaits.cpp | 80 RegCounters UsedRegs; member in __anon9d0a2eb50111::SIInsertWaits
351 UsedRegs[j] = Limit; in pushInstruction()
476 increaseCounters(Result, UsedRegs[j]); in handleOperands()
529 memset(&UsedRegs, 0, sizeof(UsedRegs)); in runOnMachineFunction()
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| /external/llvm-project/llvm/lib/MCA/Stages/ |
| D | DispatchStage.cpp | 39 ArrayRef<unsigned> UsedRegs, in notifyInstructionDispatched() argument
43 HWInstructionDispatchedEvent(IR, UsedRegs, UOps)); in notifyInstructionDispatched()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/Stages/ |
| D | DispatchStage.cpp | 39 ArrayRef<unsigned> UsedRegs, in notifyInstructionDispatched() argument
43 HWInstructionDispatchedEvent(IR, UsedRegs, UOps)); in notifyInstructionDispatched()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 582 const LivePhysRegs &UsedRegs, unsigned &PopReg, in findTemporariesForLR() argument
586 if (!UsedRegs.contains(Reg)) { in findTemporariesForLR()
653 LivePhysRegs UsedRegs(TRI); in emitPopSpecialFixUp() local
654 UsedRegs.addLiveOuts(MBB); in emitPopSpecialFixUp()
661 UsedRegs.addReg(CSRegs[i]); in emitPopSpecialFixUp()
670 UsedRegs.stepBackward(*--InstUpToMBBI); in emitPopSpecialFixUp()
694 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg); in emitPopSpecialFixUp()
704 UsedRegs.stepBackward(*PrevMBBI); in emitPopSpecialFixUp()
705 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg); in emitPopSpecialFixUp()
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| D | ARMFastISel.cpp | 230 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2034 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, in FinishCall() argument
2061 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2062 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2080 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2284 SmallVector<Register, 4> UsedRegs; in ARMEmitLibcall() local
2285 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; in ARMEmitLibcall()
2288 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in ARMEmitLibcall()
2428 SmallVector<Register, 4> UsedRegs; in SelectCall() local
2429 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) in SelectCall()
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 584 const LivePhysRegs &UsedRegs, unsigned &PopReg, in findTemporariesForLR() argument
588 if (!UsedRegs.contains(Reg)) { in findTemporariesForLR()
655 LivePhysRegs UsedRegs(TRI); in emitPopSpecialFixUp() local
656 UsedRegs.addLiveOuts(MBB); in emitPopSpecialFixUp()
663 UsedRegs.addReg(CSRegs[i]); in emitPopSpecialFixUp()
672 UsedRegs.stepBackward(*--InstUpToMBBI); in emitPopSpecialFixUp()
696 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg); in emitPopSpecialFixUp()
706 UsedRegs.stepBackward(*PrevMBBI); in emitPopSpecialFixUp()
707 findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg); in emitPopSpecialFixUp()
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| D | ARMFastISel.cpp | 229 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2021 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, in FinishCall() argument
2048 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2049 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2067 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2281 SmallVector<Register, 4> UsedRegs; in ARMEmitLibcall() local
2282 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; in ARMEmitLibcall()
2285 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in ARMEmitLibcall()
2423 SmallVector<Register, 4> UsedRegs; in SelectCall() local
2424 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) in SelectCall()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 38 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
63 UsedRegs[*AI / 32] |= 1 << (*AI & 31); in MarkAllocated()
68 UsedRegs[*AI / 32] &= ~(1 << (*AI & 31)); in MarkUnallocated()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 467 LivePhysRegs UsedRegs(STI.getRegisterInfo()); in emitPopSpecialFixUp() local
468 UsedRegs.addLiveOuts(MBB); in emitPopSpecialFixUp()
476 UsedRegs.addReg(CSRegs[i]); in emitPopSpecialFixUp()
485 UsedRegs.stepBackward(*--InstUpToMBBI); in emitPopSpecialFixUp()
505 if (!UsedRegs.contains(Register)) { in emitPopSpecialFixUp()
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| D | ARMFastISel.cpp | 200 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2016 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, in FinishCall() argument
2043 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2044 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2062 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2269 SmallVector<unsigned, 4> UsedRegs; in ARMEmitLibcall() local
2270 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; in ARMEmitLibcall()
2273 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in ARMEmitLibcall()
2414 SmallVector<unsigned, 4> UsedRegs; in SelectCall() local
2415 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) in SelectCall()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 833 SmallVector<unsigned, 8> UsedRegs; in EmitMachineNode() local
842 UsedRegs.push_back(Reg); in EmitMachineNode()
851 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); in EmitMachineNode()
859 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
867 UsedRegs.push_back(Reg); in EmitMachineNode()
873 if (!UsedRegs.empty() || II.getImplicitDefs()) in EmitMachineNode()
874 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); in EmitMachineNode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 930 SmallVector<Register, 8> UsedRegs; in EmitMachineNode() local
939 UsedRegs.push_back(Reg); in EmitMachineNode()
948 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); in EmitMachineNode()
956 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
964 UsedRegs.push_back(Reg); in EmitMachineNode()
970 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef()) in EmitMachineNode()
971 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); in EmitMachineNode()
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| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 38 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
64 UsedRegs[*AI/32] |= 1 << (*AI&31); in MarkAllocated()
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| D | MachineBasicBlock.cpp | 766 SmallVector<unsigned, 4> UsedRegs; in SplitCriticalEdge() local
778 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end()) in SplitCriticalEdge()
779 UsedRegs.push_back(Reg); in SplitCriticalEdge()
919 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); in SplitCriticalEdge()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 37 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
64 UsedRegs[*AI/32] |= 1 << (*AI&31); in MarkAllocated()
|
| D | MachineBasicBlock.cpp | 921 SmallVector<unsigned, 4> UsedRegs; in SplitCriticalEdge() local
933 if (!is_contained(UsedRegs, Reg)) in SplitCriticalEdge()
934 UsedRegs.push_back(Reg); in SplitCriticalEdge()
1068 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); in SplitCriticalEdge()
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| /external/llvm-project/llvm/lib/CodeGen/LiveDebugValues/ |
| D | VarLocBasedImpl.cpp | 721 SmallVectorImpl<uint32_t> &UsedRegs) const;
922 SmallVectorImpl<uint32_t> &UsedRegs) const { in getUsedRegs()
934 assert((UsedRegs.empty() || FoundReg != UsedRegs.back()) && in getUsedRegs()
936 UsedRegs.push_back(FoundReg); in getUsedRegs()
1237 SmallVector<uint32_t, 32> UsedRegs; in transferRegisterDef() local
1238 getUsedRegs(OpenRanges.getVarLocs(), UsedRegs); in transferRegisterDef()
1239 for (uint32_t Reg : UsedRegs) { in transferRegisterDef()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 997 SmallVector<Register, 8> UsedRegs; in EmitMachineNode() local
1006 UsedRegs.push_back(Reg); in EmitMachineNode()
1015 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); in EmitMachineNode()
1023 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
1031 UsedRegs.push_back(Reg); in EmitMachineNode()
1037 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef()) in EmitMachineNode()
1038 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); in EmitMachineNode()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 206 SmallVector<uint32_t, 16> UsedRegs; variable
291 return UsedRegs[Reg/32] & (1 << (Reg&31)); in isAllocated()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 203 SmallVector<uint32_t, 16> UsedRegs; variable
278 return UsedRegs[Reg / 32] & (1 << (Reg & 31)); in isAllocated()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 203 SmallVector<uint32_t, 16> UsedRegs; variable
286 return UsedRegs[Reg/32] & (1 << (Reg&31)); in isAllocated()
|