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/external/llvm-project/llvm/test/MC/Hexagon/
Dv62_all.s5 V0.b=vsplat(R0)
10 V0.h=vsplat(R0)
30 V0.b=vadd(V0.b,V0.b):sat
40 V0.w=vadd(V0.w,V0.w,Q0):carry
45 V0.h=vadd(vclb(V0.h),V0.h)
50 V0.w=vadd(vclb(V0.w),V0.w)
55 V1:0.w+=vadd(V0.h,V0.h)
60 V1:0.h+=vadd(V0.ub,V0.ub)
65 V0.ub=vadd(V0.ub,V0.b):sat
70 V1:0.w+=vadd(V0.uh,V0.uh)
[all …]
Dv65_all.s11 V0.uw+=vmpye(V0.uh,R0.uh)
16 if (Q0) vtmp.w=vgather(R0,M0,V0.w).w
21 vscatter(R0,M0,V0.w).w=V0
26 vscatter(R0,M0,V0.h).h=V0
31 V0.h=vlut4(V0.uh,R1:0.h)
46 vtmp.h=vgather(R0,M0,V0.h).h
51 vscatter(R0,M0,V1:0.w).h=V0
61 vscatter(R0,M0,V1:0.w).h+=V0
71 V0.ub=vasr(V0.uh,V0.uh,R0):rnd:sat
76 vscatter(R0,M0,V0.h).h+=V0
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Darmv8a-fpmul.s13 FMLAL V0.2S, V1.2H, V2.2H
14 FMLSL V0.2S, V1.2H, V2.2H
15 FMLAL V0.4S, V1.4H, V2.4H
16 FMLSL V0.4S, V1.4H, V2.4H
17 FMLAL2 V0.2S, V1.2H, V2.2H
18 FMLSL2 V0.2S, V1.2H, V2.2H
19 FMLAL2 V0.4S, V1.4H, V2.4H
20 FMLSL2 V0.4S, V1.4H, V2.4H
59 fmlal V0.2s, v1.2h, v2.h[7]
60 fmlsl V0.2s, v1.2h, v2.h[7]
[all …]
Darmv8a-fpmul-error.s7 fmlal V0.2s, v1.2h, v2.h[8]
8 fmlsl V0.2s, v1.2h, v2.h[8]
9 fmlal V0.4s, v1.4h, v2.h[8]
10 fmlsl V0.4s, v1.4h, v2.h[8]
12 fmlal2 V0.2s, v1.2h, v2.h[8]
13 fmlsl2 V0.2s, v1.2h, v2.h[8]
14 fmlal2 V0.4s, v1.4h, v2.h[8]
15 fmlsl2 V0.4s, v1.4h, v2.h[8]
17 fmlal V0.2s, v1.2h, v2.h[-1]
18 fmlsl2 V0.2s, v1.2h, v2.h[-1]
/external/guava/guava/src/com/google/common/collect/
DMultimapBuilder.java64 public abstract class MultimapBuilder<K0, V0> {
372 public <V0> SortedSetMultimapBuilder<K0, V0> treeSetValues(final Comparator<V0> comparator) {
374 return new SortedSetMultimapBuilder<K0, V0>() {
376 public <K extends K0, V extends V0> SortedSetMultimap<K, V> build() {
384 public <V0 extends Enum<V0>> SetMultimapBuilder<K0, V0> enumSetValues(
385 final Class<V0> valueClass) {
387 return new SetMultimapBuilder<K0, V0>() {
389 public <K extends K0, V extends V0> SetMultimap<K, V> build() {
393 Supplier<Set<V>> factory = (Supplier) new EnumSetSupplier<V0>(valueClass);
401 public abstract <K extends K0, V extends V0> Multimap<K, V> build();
[all …]
/external/guava/android/guava/src/com/google/common/collect/
DMultimapBuilder.java64 public abstract class MultimapBuilder<K0, V0> {
372 public <V0> SortedSetMultimapBuilder<K0, V0> treeSetValues(final Comparator<V0> comparator) {
374 return new SortedSetMultimapBuilder<K0, V0>() {
376 public <K extends K0, V extends V0> SortedSetMultimap<K, V> build() {
384 public <V0 extends Enum<V0>> SetMultimapBuilder<K0, V0> enumSetValues(
385 final Class<V0> valueClass) {
387 return new SetMultimapBuilder<K0, V0>() {
389 public <K extends K0, V extends V0> SetMultimap<K, V> build() {
393 Supplier<Set<V>> factory = (Supplier) new EnumSetSupplier<V0>(valueClass);
401 public abstract <K extends K0, V extends V0> Multimap<K, V> build();
[all …]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dfold-broadcast.mlir9 …// CHECK: %[[V0:.*]] = "tf.Mul"(%arg0, %arg1) : (tensor<5x7xf32>, tensor<7xf32>) -> tensor<5x7xf32>
10 // CHECK: %[[V0]] : tensor<5x7xf32>
19 …// CHECK: %[[V0:.*]] = "tf.Mul"(%arg0, %arg1) : (tensor<7xf32>, tensor<5x7xf32>) -> tensor<5x7xf32>
20 // CHECK: %[[V0]] : tensor<5x7xf32>
29 …// CHECK: %[[V0:.*]] = "tf.AddV2"(%arg0, %arg1) : (tensor<5x1xf32>, tensor<7xf32>) -> tensor<5x7xf…
30 // CHECK: %[[V0]] : tensor<5x7xf32>
40 …// CHECK: %[[V0:.*]] = "tf.BroadcastTo"(%arg1, %[[C0]]) : (tensor<5xf32>, tensor<3xi32>) -> tensor…
41 …// CHECK: %[[V1:.*]] = "tf.Mul"(%arg0, %[[V0]]) : (tensor<5x7xf32>, tensor<3x5x7xf32>) -> tensor<3…
51 …// CHECK: %[[V0:.*]] = "tf.Equal"(%arg0, %arg1) {incompatible_shape_error = true} : (tensor<5x7xf3…
52 // CHECK: %[[V0]] : tensor<5x7xi1>
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_overlap_add1.s64 SQNEG V0.4S, V3.4S
66 UZP1 V31.8H, V0.8H, V0.8H
67 UZP2 V30.8H, V0.8H, V0.8H
129 SQNEG V0.4S, V3.4S
130 UZP1 V1.8H, V0.8H, V0.8H
131 UZP2 V0.8H, V0.8H, V0.8H
133 REV64 V0.8h, V0.8h
163 SMLAL V12.4S, V0.4H, V3.4H
186 SQNEG V0.4S, V6.4S
191 UZP1 V1.8H, V0.8H, V0.8H
[all …]
Dixheaacd_overlap_add2.s59 LD2 {V0.4H, V1.4H}, [X10], #16
78 UMULL V23.4S, V0.4H, V2.4H
95 LD2 {V0.4H, V1.4H}, [X10], #16
100 UMULL V23.4S, V0.4H, V2.4H
184 REV64 V0.4S, V6.4S
185 SQNEG V0.4S, V0.4S
188 UZP1 V1.8H, V0.8H, V0.8H
189 UZP2 V0.8H, V0.8H, V0.8H
191 REV64 V0.4S, V0.4S
201 SMLAL V23.4S, V0.4H, V3.4H
[all …]
Dixheaacd_no_lap1.s61 LD1 {V0.4S}, [X6], X8
62 SQNEG V0.4S, V0.4S
65 SQSHL V25.4S, V0.4S, V31.4S
78 LD1 {V0.4S}, [X6], X8
82 SQNEG V0.4S, V0.4S
90 SQSHL V25.4S, V0.4S, V31.4S
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dwiden-ext.ll6 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
7 ; CHECK: v[[V1:[0-9]+]]:[[V2:[0-9]+]].h = vunpack(v[[V0]].b)
19 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
20 ; CHECK: v[[V1:[0-9]+]]:[[V2:[0-9]+]].h = vunpack(v[[V0]].b)
32 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
33 ; CHECK: v[[V1:[0-9]+]]:[[V2:[0-9]+]].h = vunpack(v[[V0]].b)
44 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
45 ; CHECK: v[[V1:[0-9]+]]:[[V2:[0-9]+]].h = vunpack(v[[V0]].b)
59 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
60 ; CHECK: v[[V1:[0-9]+]]:[[V2:[0-9]+]].w = vunpack(v[[V0]].h)
[all …]
Dwiden-trunc.ll8 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
9 ; CHECK: v[[V1:[0-9]+]].b = vdeal(v[[V0]].b)
22 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
23 ; CHECK: v[[V1:[0-9]+]].b = vdeale({{.*}},v[[V0]].b)
36 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
37 ; CHECK: v[[V1:[0-9]+]].b = vdeal(v[[V0]].b)
49 ; CHECK-DAG: v[[V0:[0-9]+]] = vmem(r0+#0)
52 ; CHECK: v[[V2:[0-9]+]].h = vpacke(v[[V1]].w,v[[V0]].w)
65 ; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
66 ; CHECK: v[[V1:[0-9]+]].h = vdeal(v[[V0]].h)
[all …]
/external/llvm-project/clang/test/CodeGenObjC/
Dweak-in-c-struct.m20 // ARM64: %[[V0:.*]] = bitcast %[[STRUCT_WEAK]]* %[[T]] to i8**
21 // ARM64: call void @__default_constructor_8_w8(i8** %[[V0]])
29 // ARM64: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
30 // ARM64: %[[V1]] = bitcast i8** %[[V0]] to i8*
39 // ARM64: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
40 // ARM64: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
58 // ARM64: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
60 // ARM64: %[[V2:.*]] = bitcast i8** %[[V0]] to i32*
64 // ARM64: %[[V5:.*]] = bitcast i8** %[[V0]] to i8*
84 // ARM64: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
[all …]
Dstrong-in-c-struct.m110 // CHECK: %[[V0:.*]] = bitcast %[[STRUCT_STRONGOUTER]]* %[[T]] to i8**
111 // CHECK: call void @__default_constructor_8_S_s16_s24(i8** %[[V0]])
119 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
120 // CHECK: call void @__default_constructor_8_s16(i8** %[[V0]])
121 // CHECK: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
131 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
132 // CHECK: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
142 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
143 // CHECK: call void @__destructor_8_s16(i8** %[[V0]])
144 // CHECK: %[[V1:.*]] = bitcast i8** %[[V0]] to i8*
[all …]
Dnontrivial-c-struct-within-struct-name.m28 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
29 // CHECK: call void @__destructor_8_S_s0(i8** %[[V0]])
35 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
36 // CHECK: call void @__destructor_8_s0(i8** %[[V0]])
42 // CHECK: %[[V0:.*]] = load i8**, i8*** %[[DST_ADDR]], align 8
43 // CHECK: call void @llvm.objc.storeStrong(i8** %[[V0]], i8* null)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp71 unsigned V0, V1; in initGlobalBaseReg() local
77 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
88 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
102 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
117 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
144 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
145 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
[all …]
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DDataMov.cpp299 static constexpr uint64_t V0 = 0xAAAAAAAAAAAAAAAAull; \ in TEST_F()
306 test.setQwordTo(T0, V0); \ in TEST_F()
315 static constexpr uint64_t V0 = 0xAAAAAAAAAAAAAAAAull; \ in TEST_F()
320 test.setQwordTo(T0, (V0 & ~Mask##Size) | Value); \ in TEST_F()
362 static constexpr uint64_t V0 = 0xAAAAAAAAAAAAAAAAull; \ in TEST_F()
369 test.setQwordTo(T0, V0); \ in TEST_F()
379 static constexpr uint64_t V0 = 0xC0BEBEEF & Mask##Size; \ in TEST_F()
384 test.setQwordTo(T0, V0); \ in TEST_F()
447 const uint32_t V0 = Value1; \ in TEST_F()
455 test.setDwordTo(T0, V0); \ in TEST_F()
[all …]
DXmmArith.cpp27 const Type V0 = Value0; \ in TEST_F()
37 test.setQwordTo(T0, static_cast<double>(V0)); \ in TEST_F()
40 test.setDwordTo(T0, static_cast<float>(V0)); \ in TEST_F()
46 ASSERT_DOUBLE_EQ(V0 Op V1, test.Dst<Type>()) << TestString; \ in TEST_F()
60 const Type V0 = Value0; \ in TEST_F()
69 test.setQwordTo(T0, static_cast<double>(V0)); \ in TEST_F()
72 test.setDwordTo(T0, static_cast<float>(V0)); \ in TEST_F()
78 ASSERT_DOUBLE_EQ(V0 Op V1, test.Dst<Type>()) << TestString; \ in TEST_F()
130 const Dqword V0 Value0; \ in TEST_F()
140 test.setDqwordTo(T0, V0); \ in TEST_F()
[all …]
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DDataMov.cpp205 const uint32_t V0 = Imm; \ in TEST_F()
208 test.setDwordTo(T0, V0); \ in TEST_F()
218 const uint32_t V0 = Imm; \ in TEST_F()
221 test.setDwordTo(T0, V0); \ in TEST_F()
295 const uint32_t V0 = Imm; \ in TEST_F()
298 test.setDwordTo(T0, V0); \ in TEST_F()
309 const uint32_t V0 = Imm; \ in TEST_F()
312 test.setDwordTo(T0, V0); \ in TEST_F()
377 const Type V0 = Value; \ in TEST_F()
384 test.setQwordTo(T0, static_cast<double>(V0)); \ in TEST_F()
[all …]
DXmmArith.cpp27 const Type V0 = Value0; \ in TEST_F()
40 test.setQwordTo(T0, static_cast<double>(V0)); \ in TEST_F()
43 test.setDwordTo(T0, static_cast<float>(V0)); \ in TEST_F()
49 ASSERT_DOUBLE_EQ(V0 Op V1, test.Dst<Type>()) << TestString; \ in TEST_F()
63 const Type V0 = Value0; \ in TEST_F()
74 test.setQwordTo(T0, static_cast<double>(V0)); \ in TEST_F()
77 test.setDwordTo(T0, static_cast<float>(V0)); \ in TEST_F()
83 ASSERT_DOUBLE_EQ(V0 Op V1, test.Dst<Type>()) << TestString; \ in TEST_F()
129 const Dqword V0 Value0; \ in TEST_F()
140 test.setDqwordTo(T0, V0); \ in TEST_F()
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp76 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() local
87 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
101 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
116 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
118 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
143 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
144 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
146 .addReg(Mips::V0).addReg(Mips::T9); in initGlobalBaseReg()
/external/llvm-project/clang/test/CodeGen/
Dvector.cpp8 int4 test1(uint4 V0) { in test1() argument
11 int4 V = !V0; in test1()
16 int4 test2(float4 V0, float4 V1) { in test2() argument
19 int4 V = !V0; in test2()
/external/scrypt/lib/crypto/
Dcrypto_scrypt-neon.c196 void * B0, * V0, * XY0; in crypto_scrypt() local
235 if ((errno = posix_memalign(&V0, 64, 128 * r * N)) != 0) in crypto_scrypt()
237 V = (uint32_t *)(V0); in crypto_scrypt()
247 if ((V0 = malloc(128 * r * N + 63)) == NULL) in crypto_scrypt()
249 V = (uint32_t *)(((uintptr_t)(V0) + 63) & ~ (uintptr_t)(63)); in crypto_scrypt()
253 if ((V0 = mmap(NULL, 128 * r * N, PROT_READ | PROT_WRITE, in crypto_scrypt()
261 V = (uint32_t *)(V0); in crypto_scrypt()
286 if (munmap(V0, 128 * r * N)) in crypto_scrypt()
289 free(V0); in crypto_scrypt()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dlds_atomic_f32.ll11 ; GCN-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
12 ; GCN: ds_add_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32
13 ; GCN: ds_add_f32 [[V3:v[0-9]+]], [[V0]] offset:64
32 ; GCN-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
33 ; GCN: ds_min_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32
34 ; GCN: ds_min_f32 [[V3:v[0-9]+]], [[V0]] offset:64
53 ; GCN-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32
55 ; GCN: ds_max_f32 [[V3:v[0-9]+]], [[V0]] offset:64
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dextract.ll13 %V0 = extractelement <2 x double> %LD, i32 0
17 %A0 = fadd double %V0, 0.0
31 %V0 = extractelement <2 x double> %LD, i32 0
35 %A0 = fadd double %V0, 1.2
49 %V0 = extractelement <4 x double> %LD, i32 0 ; <--- invalid size.
53 %A0 = fadd double %V0, 5.5

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