1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef V2M_DEF_H 7 #define V2M_DEF_H 8 9 #include <lib/utils_def.h> 10 11 /* V2M motherboard system registers & offsets */ 12 #define V2M_SYSREGS_BASE UL(0x1c010000) 13 #define V2M_SYS_ID UL(0x0) 14 #define V2M_SYS_SWITCH UL(0x4) 15 #define V2M_SYS_LED UL(0x8) 16 #define V2M_SYS_NVFLAGS UL(0x38) 17 #define V2M_SYS_NVFLAGSSET UL(0x38) 18 #define V2M_SYS_NVFLAGSCLR UL(0x3c) 19 #define V2M_SYS_CFGDATA UL(0xa0) 20 #define V2M_SYS_CFGCTRL UL(0xa4) 21 #define V2M_SYS_CFGSTATUS UL(0xa8) 22 23 #define V2M_CFGCTRL_START BIT_32(31) 24 #define V2M_CFGCTRL_RW BIT_32(30) 25 #define V2M_CFGCTRL_FUNC_SHIFT 20 26 #define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT) 27 #define V2M_FUNC_CLK_GEN U(0x01) 28 #define V2M_FUNC_TEMP U(0x04) 29 #define V2M_FUNC_DB_RESET U(0x05) 30 #define V2M_FUNC_SCC_CFG U(0x06) 31 #define V2M_FUNC_SHUTDOWN U(0x08) 32 #define V2M_FUNC_REBOOT U(0x09) 33 34 /* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */ 35 #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) 36 37 /* 38 * V2M sysled bit definitions. The values written to this 39 * register are defined in arch.h & runtime_svc.h. Only 40 * used by the primary cpu to diagnose any cold boot issues. 41 * 42 * SYS_LED[0] - Security state (S=0/NS=1) 43 * SYS_LED[2:1] - Exception Level (EL3-EL0) 44 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 45 * 46 */ 47 #define V2M_SYS_LED_SS_SHIFT 0x0 48 #define V2M_SYS_LED_EL_SHIFT 0x1 49 #define V2M_SYS_LED_EC_SHIFT 0x3 50 51 #define V2M_SYS_LED_SS_MASK U(0x1) 52 #define V2M_SYS_LED_EL_MASK U(0x3) 53 #define V2M_SYS_LED_EC_MASK U(0x1f) 54 55 /* V2M sysid register bits */ 56 #define V2M_SYS_ID_REV_SHIFT 28 57 #define V2M_SYS_ID_HBI_SHIFT 16 58 #define V2M_SYS_ID_BLD_SHIFT 12 59 #define V2M_SYS_ID_ARCH_SHIFT 8 60 #define V2M_SYS_ID_FPGA_SHIFT 0 61 62 #define V2M_SYS_ID_REV_MASK U(0xf) 63 #define V2M_SYS_ID_HBI_MASK U(0xfff) 64 #define V2M_SYS_ID_BLD_MASK U(0xf) 65 #define V2M_SYS_ID_ARCH_MASK U(0xf) 66 #define V2M_SYS_ID_FPGA_MASK U(0xff) 67 68 #define V2M_SYS_ID_BLD_LENGTH 4 69 70 71 /* NOR Flash */ 72 #define V2M_FLASH0_BASE UL(0x08000000) 73 #define V2M_FLASH0_SIZE UL(0x04000000) 74 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 75 76 #define V2M_IOFPGA_BASE UL(0x1c000000) 77 #define V2M_IOFPGA_SIZE UL(0x03000000) 78 79 /* PL011 UART related constants */ 80 #define V2M_IOFPGA_UART0_BASE UL(0x1c090000) 81 #define V2M_IOFPGA_UART1_BASE UL(0x1c0a0000) 82 #define V2M_IOFPGA_UART2_BASE UL(0x1c0b0000) 83 #define V2M_IOFPGA_UART3_BASE UL(0x1c0c0000) 84 85 #define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 86 #define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 87 #define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000 88 #define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 89 90 /* SP804 timer related constants */ 91 #define V2M_SP804_TIMER0_BASE UL(0x1C110000) 92 #define V2M_SP804_TIMER1_BASE UL(0x1C120000) 93 94 /* SP810 controller */ 95 #define V2M_SP810_BASE UL(0x1c020000) 96 #define V2M_SP810_CTRL_TIM0_SEL BIT_32(15) 97 #define V2M_SP810_CTRL_TIM1_SEL BIT_32(17) 98 #define V2M_SP810_CTRL_TIM2_SEL BIT_32(19) 99 #define V2M_SP810_CTRL_TIM3_SEL BIT_32(21) 100 101 /* 102 * The flash can be mapped either as read-only or read-write. 103 * 104 * If it is read-write then it should also be mapped as device memory because 105 * NOR flash programming involves sending a fixed, ordered sequence of commands. 106 * 107 * If it is read-only then it should also be mapped as: 108 * - Normal memory, because reading from NOR flash is transparent, it is like 109 * reading from RAM. 110 * - Non-executable by default. If some parts of the flash need to be executable 111 * then platform code is responsible for re-mapping the appropriate portion 112 * of it as executable. 113 */ 114 #define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 115 V2M_FLASH0_SIZE, \ 116 MT_DEVICE | MT_RW | MT_SECURE) 117 118 #define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 119 V2M_FLASH0_SIZE, \ 120 MT_RO_DATA | MT_SECURE) 121 122 #define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\ 123 V2M_IOFPGA_SIZE, \ 124 MT_DEVICE | MT_RW | MT_SECURE) 125 126 /* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */ 127 #define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \ 128 V2M_IOFPGA_BASE, \ 129 V2M_IOFPGA_SIZE, \ 130 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 131 132 133 #endif /* V2M_DEF_H */ 134