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Searched refs:V62 (Results 1 – 25 of 27) sorted by relevance

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/external/llvm-project/llvm/test/MC/Hexagon/
Dv62a_regs.s1 …xagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-V62
11 # CHECK-V62: 6a10c000 { r0 = framelimit }
12 # CHECK-V62: 6a11c000 { r0 = framekey }
13 # CHECK-V62: 6810c000 { r1:0 = c17:16 }
23 # CHECK-V62: 6a12c000 { r0 = pktcountlo }
24 # CHECK-V62: 6a13c000 { r0 = pktcounthi }
25 # CHECK-V62: 6812c000 { r1:0 = c19:18 }
26 # CHECK-V62: 6812c000 { r1:0 = c19:18 }
37 # CHECK-V62: 6a1ec000 { r0 = utimerlo }
38 # CHECK-V62: 6a1fc000 { r0 = utimerhi }
[all …]
DJ2_trap1_dep.s1 …nv62 -filetype=obj %s | llvm-objdump --mcpu=hexagonv62 -d - | FileCheck %s --check-prefix=CHECK-V62
4 # CHECK-V62: trap1(#0)
Delf-flags.s4 …nv62 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V62 %s
9 # CHECK-V62: Flags: 0x62
/external/llvm-project/clang/include/clang/Basic/
DBuiltinsHexagon.def26 #pragma push_macro("V62")
27 #define V62 "v62|" V65
29 #define V60 "v60|" V62
97 TARGET_BUILTIN(__builtin_HEXAGON_A6_vminub_RdP,"LLiLLiLLi","", V62)
130 #pragma pop_macro("V62")
DBuiltinsHexagonDep.def875 // V62 Scalar Instructions.
877 TARGET_BUILTIN(__builtin_HEXAGON_M6_vabsdiffb, "LLiLLiLLi", "", V62)
878 TARGET_BUILTIN(__builtin_HEXAGON_M6_vabsdiffub, "LLiLLiLLi", "", V62)
879 TARGET_BUILTIN(__builtin_HEXAGON_S6_vsplatrbp, "LLii", "", V62)
880 TARGET_BUILTIN(__builtin_HEXAGON_S6_vtrunehb_ppp, "LLiLLiLLi", "", V62)
881 TARGET_BUILTIN(__builtin_HEXAGON_S6_vtrunohb_ppp, "LLiLLiLLi", "", V62)
1532 // V62 HVX Instructions.
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepArch.h21 enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67 }; enumerator
40 {"hexagonv62", Hexagon::ArchEnum::V62},
DHexagonDepArch.td17 …btargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architec…
DHexagonSubtarget.h159 return getHexagonArchVersion() >= Hexagon::ArchEnum::V62; in hasV62Ops()
162 return getHexagonArchVersion() == Hexagon::ArchEnum::V62; in hasV62OpsOnly()
204 return HexagonHVXVersion >= Hexagon::ArchEnum::V62; in useHVXV62Ops()
DHexagonIICScalar.td10 // classes as per V62. Currently, they are just extracted from
DHexagonScheduleV62.td35 // Hexagon V62 Resource Definitions -
DHexagon.td39 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepArch.td15 …btargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architec…
DHexagonDepArch.h16 enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66 }; enumerator
DHexagonSubtarget.h143 return getHexagonArchVersion() >= Hexagon::ArchEnum::V62; in hasV62Ops()
146 return getHexagonArchVersion() == Hexagon::ArchEnum::V62; in hasV62OpsOnly()
DHexagonIICScalar.td10 // classes as per V62. Curretnly, they are just extracted from
DHexagonScheduleV62.td35 // Hexagon V62 Resource Definitions -
DHexagonSchedule.td77 // V62 Machine Info +
DHexagonSubtarget.cpp98 {"hexagonv62", Hexagon::ArchEnum::V62}, in initializeSubtargetDependencies()
DHexagon.td36 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dswp-check-offset.ll2 …nv62 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V62 %s
14 ; CHECK-V62-NOT: }{{[ \t]*}}:mem_noshuf
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCTargetDesc.cpp81 clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
290 case Hexagon::ArchEnum::V62: in selectHexagonFS()
/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCTargetDesc.cpp87 clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
354 case Hexagon::ArchEnum::V62: in selectHexagonFS()
/external/llvm-project/llvm/lib/Target/VE/Disassembler/
DVEDisassembler.cpp106 VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63};
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsHexagonDep.td3657 // V62 Scalar Instructions.
5593 // V62 HVX Instructions.
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsHexagon.td3964 // V62 Scalar Instructions.
5820 // V62 HVX Instructions.

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