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Searched refs:VARYING_BIT_LAYER (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_vue_map.c92 slots_valid &= ~(VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT); in brw_compute_vue_map()
Dbrw_fs_visitor.cpp577 VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PSIZ; in emit_urb_writes()
659 if (vue_map->slots_valid & VARYING_BIT_LAYER) in emit_urb_writes()
Dbrw_compiler.h1664 if ((inputs_read & (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT)) == 0) { in brw_compute_first_urb_slot_required()
/external/mesa3d/src/compiler/
Dshader_enums.h369 #define VARYING_BIT_LAYER BITFIELD64_BIT(VARYING_SLOT_LAYER) macro
/external/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_draw.c168 .layer_zero = !gs || !(gs->nir->info.outputs_written & VARYING_BIT_LAYER), in fd6_draw_vbo()
/external/mesa3d/src/freedreno/ir3/
Dir3_nir.c460 bool layer_zero = so->key.layer_zero && (s->info.inputs_read & VARYING_BIT_LAYER); in ir3_nir_lower_variant()
Dir3_shader.c360 if (info->inputs_read & VARYING_BIT_LAYER) { in ir3_setup_used_key()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shader_nir.c382 info->writes_layer = nir->info.outputs_written & VARYING_BIT_LAYER; in si_nir_scan_shader()
/external/mesa3d/src/intel/vulkan/
DgenX_pipeline.c1367 !(last->vue_map.slots_valid & VARYING_BIT_LAYER);
/external/mesa3d/src/freedreno/vulkan/
Dtu_pipeline.c2101 key.layer_zero = !(outputs_written & VARYING_BIT_LAYER); in tu_pipeline_builder_compile_shaders()
/external/mesa3d/src/mesa/drivers/dri/i965/
DgenX_state_upload.c976 if (!(vue_map->slots_valid & VARYING_BIT_LAYER)) in genX()
/external/mesa3d/src/gallium/drivers/iris/
Diris_state.c4001 if (!(vue_map->slots_valid & VARYING_BIT_LAYER)) in iris_emit_sbe_swiz()